soc: riscv: gd32vf103: use nuclei,systimer compatible

After some analysis I found out that there's no machine timer provided
by the "riscv" vendor. There are some specs for the mtime/mtimecmp
registers (this is why we can have a single driver), but the actual
register layout or implementations differ amongst vendors. GD32 uses the
Nuclei implementation, named "system timer" in their documentation. This
patch aligns with vendor specs.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

dts/bindings/timer/nuclei,systimer.yaml

@@ -1,24 +1,34 @@
 # Copyright (c) 2021 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: RISC-V Machine timer
+description: |
+  Nuclei System Timer
 
-compatible: "riscv,machine-timer"
+  The Nuclei system timer provides RISC-V privileged mtime and mtimecmp
+  registers.
+
+compatible: "nuclei,systimer"
 
 include: base.yaml
 
 properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
     clk-divider:
       type: int
       required: false
       description: |
         clk-divider specifies the division ratio to the CPU frequency that
-        clock used by machine timer.
+        clock used by the system timer.
-        This property supports the case that the machine timer and CPU use
+        This property supports the case that the system timer and CPU use
         different clock sources.
         This configuration is used sometimes for such as low power consumption.
 
-        For example, the CPU clock frequency is 108MHz, and the machine timer
+        For example, the CPU clock frequency is 108MHz, and the system timer
         uses 27MHz, which is the CPU clock divided by 4.
         In this case, the CPU clock frequency is defined in the CPU node
         as follows
@@ -32,8 +42,8 @@ properties:
            division_ratio = 2^n
            n = log_2(division_ratio)
 
-        Setting clk-divider to 2 specifies the machine timer uses the clock
+        Setting clk-divider to 2 specifies the system timer uses the clock
         that CPU clock frequency divided by (2^2=)4, or 27MHz.
 
         Devision ratio constants can be found in the
-        dt-bindings/timer/nuclei-machine-timer.h header file.
+        dt-bindings/timer/nuclei-systimer.h header file.

dts/riscv/gigadevice/gd32vf103.dtsi

@@ -5,7 +5,7 @@
  */
 
 #include <zephyr/dt-bindings/gpio/gpio.h>
-#include <zephyr/dt-bindings/timer/riscv-machine-timer.h>
+#include <zephyr/dt-bindings/timer/nuclei-systimer.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 
 #include <zephyr/dt-bindings/pwm/pwm.h>
@@ -37,11 +37,12 @@
 		compatible = "gd,gd32vf103-soc", "simple-bus";
 		ranges;
 
-		mtimer: machine-timer@d1000000 {
+		systimer: timer@d1000000 {
-			compatible = "riscv,machine-timer";
+			compatible = "nuclei,systimer";
-			reg = <0xd1000000 0x1
+			reg = <0xd1000000 0x10000>;
-			       0xd1000008 0x1>;
+			interrupts = <3 0>, <7 0>;
-			clk-divider = <RISCV_MACHINE_TIMER_DIVIDER_4>;
+			interrupt-parent = <&eclic>;
+			clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
 		};
 
 		eclic: interrupt-controller@d2000000 {

include/zephyr/dt-bindings/timer/nuclei-systimer.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021, TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_NUCLEI_SYSTIMER_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_NUCLEI_SYSTIMER_H_
+
+/* Clock divider values */
+#define NUCLEI_SYSTIMER_DIVIDER_1          0
+#define NUCLEI_SYSTIMER_DIVIDER_2          1
+#define NUCLEI_SYSTIMER_DIVIDER_4          2
+#define NUCLEI_SYSTIMER_DIVIDER_8          3
+#define NUCLEI_SYSTIMER_DIVIDER_16         4
+#define NUCLEI_SYSTIMER_DIVIDER_32         5
+#define NUCLEI_SYSTIMER_DIVIDER_64         6
+#define NUCLEI_SYSTIMER_DIVIDER_128        7
+#define NUCLEI_SYSTIMER_DIVIDER_256        8
+#define NUCLEI_SYSTIMER_DIVIDER_512        9
+#define NUCLEI_SYSTIMER_DIVIDER_1024      10
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_NUCLEI_SYSTIMER_H_ */

include/zephyr/dt-bindings/timer/riscv-machine-timer.h

@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2021, TOKITA Hiroshi <tokita.hiroshi@gmail.com>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_
-
-/* Clock divider values */
-#define RISCV_MACHINE_TIMER_DIVIDER_1          0
-#define RISCV_MACHINE_TIMER_DIVIDER_2          1
-#define RISCV_MACHINE_TIMER_DIVIDER_4          2
-#define RISCV_MACHINE_TIMER_DIVIDER_8          3
-#define RISCV_MACHINE_TIMER_DIVIDER_16         4
-#define RISCV_MACHINE_TIMER_DIVIDER_32         5
-#define RISCV_MACHINE_TIMER_DIVIDER_64         6
-#define RISCV_MACHINE_TIMER_DIVIDER_128        7
-#define RISCV_MACHINE_TIMER_DIVIDER_256        8
-#define RISCV_MACHINE_TIMER_DIVIDER_512        9
-#define RISCV_MACHINE_TIMER_DIVIDER_1024      10
-
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_ */

soc/riscv/riscv-privilege/gd32vf103/soc.h

@@ -15,7 +15,7 @@
 #include <zephyr/devicetree.h>
 
 /* Timer configuration */
-#define RISCV_MTIME_BASE      DT_REG_ADDR_BY_IDX(DT_NODELABEL(mtimer), 0)
+#define RISCV_MTIME_BASE      DT_REG_ADDR(DT_NODELABEL(systimer))
-#define RISCV_MTIMECMP_BASE   DT_REG_ADDR_BY_IDX(DT_NODELABEL(mtimer), 1)
+#define RISCV_MTIMECMP_BASE   (RISCV_MTIME_BASE + 8)
 
 #endif  /* RISCV_GD32VF103_SOC_H */