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arch: riscv32: fe310: Always-On domain adress definition

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Added always-on domain address definition

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
This commit is contained in:
Tomasz Jurtsch 2018-04-04 22:11:07 +02:00 • committed by Kumar Gala
commit 6dae38cb98
1 changed files with 12 additions and 0 deletions
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12
arch/riscv32/soc/riscv-privilege/fe310/soc.h
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@ -105,10 +105,22 @@
#define FE310_PLIC_MAX_PRIORITY 7 #define FE310_PLIC_MAX_PRIORITY 7
/* Clock controller. */
#define PRCI_BASE_ADDR 0x10008000
/* Timer configuration */ /* Timer configuration */
#define RISCV_MTIME_BASE 0x0200BFF8 #define RISCV_MTIME_BASE 0x0200BFF8
#define RISCV_MTIMECMP_BASE 0x02004000 #define RISCV_MTIMECMP_BASE 0x02004000
/* Always ON Domain */
#define FE310_PMUIE 0x10000140
#define FE310_PMUCAUSE 0x10000144
#define FE310_PMUSLEEP 0x10000148
#define FE310_PMUKEY 0x1000014C
#define FE310_SLEEP_KEY_VAL 0x0051F15E
#define FE310_BACKUP_REG_BASE 0x10000080
/* lib-c hooks required RAM defined variables */ /* lib-c hooks required RAM defined variables */
#define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR #define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR
#define RISCV_RAM_SIZE CONFIG_RISCV_RAM_SIZE #define RISCV_RAM_SIZE CONFIG_RISCV_RAM_SIZE