iwdg: make independent watchdog driver compliant with STM32Cube LL API
Appropriate inclusion done for F1/F3/F4/L4 families in SoC tree. JIRA: ZEP-2347 Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
This commit is contained in:
Adam Podogrocki
Kumar Gala
parent
46555f17e9
commit
6d4da19602
7 changed files with 160 additions and 140 deletions
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@ -48,6 +48,10 @@
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#include <stm32f1xx_ll_i2c.h>
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#endif
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#ifdef CONFIG_IWDG_STM32
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#include <stm32f1xx_ll_iwdg.h>
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#endif
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32F1_SOC_H_ */
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@ -49,6 +49,10 @@
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#include <stm32f3xx_ll_i2c.h>
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#endif
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#ifdef CONFIG_IWDG_STM32
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#include <stm32f3xx_ll_iwdg.h>
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#endif
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32F3_SOC_H_ */
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@ -52,6 +52,10 @@
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#include <stm32f4xx_ll_rng.h>
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#endif
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#ifdef CONFIG_IWDG_STM32
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#include <stm32f4xx_ll_iwdg.h>
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#endif
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/* For IMG_MANAGER */
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#if defined(CONFIG_SOC_FLASH_STM32)
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#define FLASH_DRIVER_NAME CONFIG_SOC_FLASH_STM32_DEV_NAME
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@ -47,6 +47,10 @@
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#include <stm32l4xx_ll_i2c.h>
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#endif
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#ifdef CONFIG_IWDG_STM32
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#include <stm32l4xx_ll_iwdg.h>
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#endif
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/* For IMG_MANAGER */
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#if defined(CONFIG_SOC_FLASH_STM32)
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#define FLASH_DRIVER_NAME CONFIG_SOC_FLASH_STM32_DEV_NAME
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@ -1,43 +1,21 @@
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# Kconfig - STM32 IWDG configuration
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#
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# Copyright (c) 2016 Open-RnD Sp. z o.o.
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# Copyright (c) 2017 RnDity Sp. z o.o.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_FAMILY_STM32
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config IWDG_STM32
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menuconfig IWDG_STM32
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bool "Independent Watchdog (IWDG) Driver for STM32 family of MCUs"
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depends on SOC_FAMILY_STM32
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help
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Enable IWDG driver for STM32 line of MCUs
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config IWDG_STM32_PRESCALER
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int "Prescaler divider for clock feeding the IWDG"
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depends on IWDG_STM32
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default 4
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range 4 256
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help
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Set the prescaler divider for the clock feeding the Independent
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Watchdog. Higher values indicate that the watchdog will need to
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be reloaded more frequently. Allowed values: 4, 8, 16, 32, 64,
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128, 256. This setting combined with reload counter defines the
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watchdog countdown time.
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config IWDG_STM32_RELOAD_COUNTER
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int "Value for IWDG counter"
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depends on IWDG_STM32
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default 2048
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range 0 4095
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help
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Configure the value to be loaded into the watchdog's counter each
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time a reload operation is performed. This value combined with
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prescaler setting defines the watchdog countdown time.
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config IWDG_STM32_START_AT_BOOT
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bool "Start IWDG during boot"
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depends on IWDG_STM32
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default n
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default y
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help
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Enable this setting to allow IWDG to be automatically started
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during device initialization. Note that once IWDG is started
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@ -51,4 +29,11 @@ config IWDG_STM32_DEVICE_NAME
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help
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Set the name used by IWDG device during registration.
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endif # SOC_FAMILY_STM32
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config IWDG_STM32_TIMEOUT
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int "Value for IWDG timeout in [us]"
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depends on IWDG_STM32
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default 100
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range 100 26214400
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help
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Set timeout value for IWDG in microseconds.
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The min timeout supported is 0.1ms, the max timeout is 26214.4ms.
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@ -1,36 +1,71 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2017 RnDity Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for Independent Watchdog (IWDG) for STM32 MCUs
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*
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* Based on reference manual:
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* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 19: Independent watchdog (IWDG)
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*
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*/
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#include <watchdog.h>
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#include <soc.h>
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#include <errno.h>
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#include <assert.h>
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#include "iwdg_stm32.h"
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#define AS_IWDG(__base_addr) \
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(struct iwdg_stm32 *)(__base_addr)
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/* Minimal timeout in microseconds. */
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#define IWDG_TIMEOUT_MIN 100
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/* Maximal timeout in microseconds. */
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#define IWDG_TIMEOUT_MAX 26214400
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#define IS_IWDG_TIMEOUT(__TIMEOUT__) \
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(((__TIMEOUT__) >= IWDG_TIMEOUT_MIN) && \
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((__TIMEOUT__) <= IWDG_TIMEOUT_MAX))
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/*
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* Status register need 5 RC LSI divided by prescaler clock to be updated.
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* With higher prescaler (256U), and according to HSI variation,
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* we need to wait at least 6 cycles so 48 ms.
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*/
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#define IWDG_DEFAULT_TIMEOUT 48u
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/**
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* @brief Calculates prescaler & reload values.
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*
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* @param timeout Timeout value in microseconds.
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* @param prescaler Pointer to prescaler value.
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* @param reload Pointer to reload value.
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*/
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static void iwdg_stm32_convert_timeout(u32_t timeout,
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u32_t *prescaler,
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u32_t *reload)
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{
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assert(IS_IWDG_TIMEOUT(timeout));
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u16_t divider = 0;
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u8_t shift = 0;
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/* Convert timeout to seconds. */
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float m_timeout = (float)timeout / 1000000 * LSI_VALUE;
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do {
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divider = 4 << shift;
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shift++;
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} while ((m_timeout / divider) > 0xFFF);
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/*
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* Value of the 'shift' variable corresponds to the
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* defines of LL_IWDG_PRESCALER_XX type.
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*/
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*prescaler = --shift;
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*reload = (uint32_t)(m_timeout / divider) - 1;
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}
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static void iwdg_stm32_enable(struct device *dev)
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{
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volatile struct iwdg_stm32 *iwdg = AS_IWDG(IWDG_BASE);
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IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
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ARG_UNUSED(dev);
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iwdg->kr.bit.key = STM32_IWDG_KR_START;
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LL_IWDG_Enable(iwdg);
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}
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static void iwdg_stm32_disable(struct device *dev)
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@ -40,30 +75,62 @@ static void iwdg_stm32_disable(struct device *dev)
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}
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static int iwdg_stm32_set_config(struct device *dev,
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struct wdt_config *config)
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struct wdt_config *config)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(config);
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IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
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u32_t timeout = config->timeout;
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u32_t prescaler = 0;
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u32_t reload = 0;
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u32_t tickstart;
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/* no configuration */
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assert(IS_IWDG_TIMEOUT(timeout));
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return -ENOTSUP;
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iwdg_stm32_convert_timeout(timeout, &prescaler, &reload);
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assert(IS_IWDG_PRESCALER(prescaler));
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assert(IS_IWDG_RELOAD(reload));
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LL_IWDG_EnableWriteAccess(iwdg);
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LL_IWDG_SetPrescaler(iwdg, prescaler);
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LL_IWDG_SetReloadCounter(iwdg, reload);
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#if defined(CONFIG_SOC_SERIES_STM32F3X) || defined(CONFIG_SOC_SERIES_STM32L4X)
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/* Neither STM32F1X nor STM32F4 series supports window option. */
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LL_IWDG_SetWindow(iwdg, 0x0FFF);
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#endif
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tickstart = k_uptime_get_32();
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while (LL_IWDG_IsReady(iwdg) == 0) {
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if ((k_uptime_get_32() - tickstart) > IWDG_DEFAULT_TIMEOUT) {
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return -ENODEV;
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}
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}
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LL_IWDG_ReloadCounter(iwdg);
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return 0;
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}
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static void iwdg_stm32_get_config(struct device *dev,
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struct wdt_config *config)
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struct wdt_config *config)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(config);
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IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
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u32_t prescaler = LL_IWDG_GetPrescaler(iwdg);
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u32_t reload = LL_IWDG_GetReloadCounter(iwdg);
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/* Timeout given in microseconds. */
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config->timeout = (u32_t)((4 << prescaler) * (reload + 1)
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* (1000000 / LSI_VALUE));
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}
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static void iwdg_stm32_reload(struct device *dev)
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{
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volatile struct iwdg_stm32 *iwdg = AS_IWDG(IWDG_BASE);
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IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
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ARG_UNUSED(dev);
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iwdg->kr.bit.key = STM32_IWDG_KR_RELOAD;
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LL_IWDG_ReloadCounter(iwdg);
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}
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static const struct wdt_driver_api iwdg_stm32_api = {
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@ -74,43 +141,36 @@ static const struct wdt_driver_api iwdg_stm32_api = {
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.reload = iwdg_stm32_reload,
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};
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static inline int __iwdg_stm32_prescaler(int setting)
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{
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int v;
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int i = 0;
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/* prescaler range 4 - 256 */
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for (v = 4; v < 256; v *= 2, i++) {
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if (v == setting)
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return i;
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}
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return i;
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}
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static int iwdg_stm32_init(struct device *dev)
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{
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volatile struct iwdg_stm32 *iwdg = AS_IWDG(IWDG_BASE);
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IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
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struct wdt_config config;
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/* clock setup is not required, once the watchdog is enabled
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* LSI oscillator will be forced on and fed to IWD after
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* stabilization period
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config.timeout = CONFIG_IWDG_STM32_TIMEOUT;
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LL_IWDG_Enable(iwdg);
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iwdg_stm32_set_config(dev, &config);
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/*
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* The ST production value for the option bytes where WDG_SW bit is
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* present is 0x00FF55AA, namely the Software watchdog mode is
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* enabled by default.
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* If the IWDG is started by either hardware option or software access,
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* the LSI oscillator is forced ON and cannot be disabled.
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*
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* t_IWDG(ms) = t_LSI(ms) x 4 x 2^(IWDG_PR[2:0]) x (IWDG_RLR[11:0] + 1)
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*/
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/* unlock access to configuration registers */
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iwdg->kr.bit.key = STM32_IWDG_KR_UNLOCK;
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iwdg->pr.bit.pr =
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__iwdg_stm32_prescaler(CONFIG_IWDG_STM32_PRESCALER);
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iwdg->rlr.bit.rl = CONFIG_IWDG_STM32_RELOAD_COUNTER;
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#ifdef CONFIG_IWDG_STM32_START_AT_BOOT
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iwdg_stm32_enable(dev);
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#endif
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return 0;
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}
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DEVICE_AND_API_INIT(iwdg_stm32, CONFIG_IWDG_STM32_DEVICE_NAME, iwdg_stm32_init,
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NULL, NULL,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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static struct iwdg_stm32_data iwdg_stm32_dev_data = {
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.Instance = IWDG
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};
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DEVICE_AND_API_INIT(iwdg_stm32, CONFIG_IWDG_STM32_DEVICE_NAME,
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iwdg_stm32_init, &iwdg_stm32_dev_data, NULL,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&iwdg_stm32_api);
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2017 RnDity Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,65 +13,23 @@
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/**
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* @brief Driver for Independent Watchdog (IWDG) for STM32 MCUs
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*
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* Based on reference manual:
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* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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* advanced ARM(r)-based 32-bit MCUs
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* The driver targets all STM32 SoCs. For details please refer to
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* an appropriate reference manual and look for chapter called:
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*
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* Chapter 19: Independent watchdog (IWDG)
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* Independent watchdog (IWDG)
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*
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*/
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/* counter reload trigger */
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#define STM32_IWDG_KR_RELOAD 0xaaaa
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/* magic value for unlocking write access to PR and RLR */
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#define STM32_IWDG_KR_UNLOCK 0x5555
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/* watchdog start */
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#define STM32_IWDG_KR_START 0xcccc
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/* 19.4.1 IWDG_KR */
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union __iwdg_kr {
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u32_t val;
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struct {
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u16_t key;
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u16_t rsvd;
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} bit;
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/* driver data */
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struct iwdg_stm32_data {
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/* IWDG peripheral instance. */
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IWDG_TypeDef *Instance;
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};
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/* 19.4.2 IWDG_PR */
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union __iwdg_pr {
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u32_t val;
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struct {
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u32_t pr :3 __packed;
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u32_t rsvd__3_31 :29 __packed;
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} bit;
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};
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#define IWDG_STM32_DATA(dev) \
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((struct iwdg_stm32_data * const)(dev)->driver_data)
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/* 19.4.3 IWDG_RLR */
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union __iwdg_rlr {
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u32_t val;
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struct {
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u32_t rl :12 __packed;
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u32_t rsvd__12_31 :20 __packed;
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} bit;
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};
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/* 19.4.4 IWDG_SR */
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union __iwdg_sr {
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u32_t val;
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struct {
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u32_t pvu :1 __packed;
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u32_t rvu :1 __packed;
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u32_t rsvd__2_31 :30 __packed;
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} bit;
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};
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/* 19.4.5 IWDG register map */
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struct iwdg_stm32 {
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union __iwdg_kr kr;
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union __iwdg_pr pr;
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union __iwdg_rlr rlr;
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union __iwdg_sr sr;
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};
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#define IWDG_STM32_STRUCT(dev) \
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((IWDG_TypeDef *)(IWDG_STM32_DATA(dev))->Instance)
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#endif /* _STM32_IWDG_H_ */
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