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drivers/ipm: Add IPM support for i.MX7

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This patch ads the support for the IPM drivers on i.MX7 SoC family.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
This commit is contained in:
Diego Sueiro 2018-11-19 17:42:40 +00:00 • committed by Kumar Gala
commit 6d070c77b6
4 changed files with 108 additions and 71 deletions
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10
dts/arm/nxp/nxp_imx7d_m4.dtsi
View file

@ -260,6 +260,16 @@
status = "disabled"; status = "disabled";
}; };
mub:mu@30ab0000 {
compatible = "nxp,imx-mu";
reg = <0x30ab0000 0x4000>;
interrupts = <97 0>;
rdc = <RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)>;
label = "MU_B";
status = "disabled";
};
i2c1: i2c@30a20000 { i2c1: i2c@30a20000 {
compatible = "fsl,imx7d-i2c"; compatible = "fsl,imx7d-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>; clock-frequency = <I2C_BITRATE_STANDARD>;

7
soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4
View file

@ -57,4 +57,11 @@ config PWM_IMX
endif # PWM endif # PWM
if IPM
config IPM_IMX
default y
endif # IPM
endif # SOC_MCIMX7_M4 endif # SOC_MCIMX7_M4

5
soc/arm/nxp_imx/mcimx7_m4/dts_fixup.h
View file

@ -107,4 +107,9 @@
#define DT_UART_IMX_UART_7_IRQ_PRI DT_NXP_IMX_UART_30A90000_IRQ_0_PRIORITY #define DT_UART_IMX_UART_7_IRQ_PRI DT_NXP_IMX_UART_30A90000_IRQ_0_PRIORITY
#define DT_UART_IMX_UART_7_MODEM_MODE DT_NXP_IMX_UART_30A90000_MODEM_MODE #define DT_UART_IMX_UART_7_MODEM_MODE DT_NXP_IMX_UART_30A90000_MODEM_MODE
#define DT_IPM_IMX_MU_B_BASE_ADDRESS DT_NXP_IMX_MU_30AB0000_BASE_ADDRESS
#define DT_IPM_IMX_MU_B_IRQ DT_NXP_IMX_MU_30AB0000_IRQ_0
#define DT_IPM_IMX_MU_B_IRQ_PRI DT_NXP_IMX_MU_30AB0000_IRQ_0_PRIORITY
#define DT_IPM_IMX_MU_B_NAME DT_NXP_IMX_MU_30AB0000_LABEL
/* End of SoC Level DTS fixup file */ /* End of SoC Level DTS fixup file */

15
soc/arm/nxp_imx/mcimx7_m4/soc.c
View file

@ -210,6 +210,17 @@ static void nxp_mcimx7_pwm_config(void)
} }
#endif /* CONFIG_PWM_IMX */ #endif /* CONFIG_PWM_IMX */
#ifdef CONFIG_IPM_IMX
static void nxp_mcimx7_mu_config(void)
{
/* Set access to MU B for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapMuB, MU_B_RDC, false, false);
/* Enable clock gate for MU*/
CCM_ControlGate(CCM, ccmCcgrGateMu, ccmClockNeededRun);
}
#endif /* CONFIG_IPM_IMX */
static int nxp_mcimx7_init(struct device *arg) static int nxp_mcimx7_init(struct device *arg)
{ {
ARG_UNUSED(arg); ARG_UNUSED(arg);
@ -236,6 +247,10 @@ static int nxp_mcimx7_init(struct device *arg)
nxp_mcimx7_pwm_config(); nxp_mcimx7_pwm_config();
#endif /* CONFIG_PWM_IMX */ #endif /* CONFIG_PWM_IMX */
#ifdef CONFIG_IPM_IMX
nxp_mcimx7_mu_config();
#endif /* CONFIG_IPM_IMX */
return 0; return 0;
} }