soc/intel_adsp: Fix "noinit" section cacheability

This section was being put in the wrong region, and was in L1-cached
incoherent memory.  That's wrong, as users are expected to expressly
ask for "__incoherent" memory and do manual cache management if
required.  Default memory of all types should be uncached and
coherent.

Very few spots use this and cache effects tend to be ephemeral, so it
was somewhat obscure.  It was discovered via an SMP race when using
logging very close to system start where the log thread on the second
CPU will race with messages added on the first -- log messages are
stored in a __noinit mem_slab.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>

soc/xtensa/intel_adsp/cavs_v15/linker.ld

@@ -411,12 +411,6 @@ SECTIONS
     KEEP (*(.fw_ready_metadata))
   } >ram :ram_phdr
 
-  .noinit : ALIGN(4)
-  {
-    *(.noinit)
-    *(.noinit.*)
-  } >ram :ram_phdr
-
   .lit4 : ALIGN(4)
   {
     _lit4_start = ABSOLUTE(.);
@@ -447,6 +441,12 @@ SECTIONS
     . = ALIGN(4096);
   } >ucram :ucram_phdr
 
+  .noinit : ALIGN(4)
+  {
+    *(.noinit)
+    *(.noinit.*)
+  } >ucram :ucram_phdr
+
 /* These values need to change in our scheme, where the common-ram
  * sections need to be linked in safe/uncached memory but common-rom
  * wants to use the cache