From 6cc08fc190349a98e56104f1a3be861c8f842153 Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Thu, 29 Oct 2020 15:17:39 -0700 Subject: [PATCH] soc/intel_adsp: Fix "noinit" section cacheability This section was being put in the wrong region, and was in L1-cached incoherent memory. That's wrong, as users are expected to expressly ask for "__incoherent" memory and do manual cache management if required. Default memory of all types should be uncached and coherent. Very few spots use this and cache effects tend to be ephemeral, so it was somewhat obscure. It was discovered via an SMP race when using logging very close to system start where the log thread on the second CPU will race with messages added on the first -- log messages are stored in a __noinit mem_slab. Signed-off-by: Andy Ross --- soc/xtensa/intel_adsp/cavs_v15/linker.ld | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld index 08c9d08b7f9..a7044ae04be 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld @@ -411,12 +411,6 @@ SECTIONS KEEP (*(.fw_ready_metadata)) } >ram :ram_phdr - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >ram :ram_phdr - .lit4 : ALIGN(4) { _lit4_start = ABSOLUTE(.); @@ -447,6 +441,12 @@ SECTIONS . = ALIGN(4096); } >ucram :ucram_phdr + .noinit : ALIGN(4) + { + *(.noinit) + *(.noinit.*) + } >ucram :ucram_phdr + /* These values need to change in our scheme, where the common-ram * sections need to be linked in safe/uncached memory but common-rom * wants to use the cache