diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld
index 08c9d08b7f9..a7044ae04be 100644
--- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld
+++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld
@@ -411,12 +411,6 @@ SECTIONS
     KEEP (*(.fw_ready_metadata))
   } >ram :ram_phdr
 
-  .noinit : ALIGN(4)
-  {
-    *(.noinit)
-    *(.noinit.*)
-  } >ram :ram_phdr
-
   .lit4 : ALIGN(4)
   {
     _lit4_start = ABSOLUTE(.);
@@ -447,6 +441,12 @@ SECTIONS
     . = ALIGN(4096);
   } >ucram :ucram_phdr
 
+  .noinit : ALIGN(4)
+  {
+    *(.noinit)
+    *(.noinit.*)
+  } >ucram :ucram_phdr
+
 /* These values need to change in our scheme, where the common-ram
  * sections need to be linked in safe/uncached memory but common-rom
  * wants to use the cache