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spi_nxp_lpspi: Move DMA-based code to own file

Browse source 
The DMA-based path of the lpspi driver is basically
almost a driver of it's own, move it to it's own file.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder 2024-12-09 14:53:25 -06:00 • committed by Benjamin Cabé
commit 6cbe52b23c
5 changed files with 427 additions and 377 deletions
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1
drivers/spi/spi_nxp_lpspi/CMakeLists.txt
View file

@ -2,4 +2,5 @@
zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI spi_nxp_lpspi_common.c)
zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI_NORMAL spi_mcux_lpspi.c)
zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI_DMA spi_nxp_lpspi_dma.c)
zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI_RTIO spi_mcux_lpspi_rtio.c)

2
drivers/spi/spi_nxp_lpspi/Kconfig
View file

@ -16,6 +16,7 @@ if !SPI_RTIO
config SPI_MCUX_LPSPI_DMA
bool "MCUX LPSPI SPI DMA Support"
select DMA
depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NXP_LPSPI),dmas)
help
Enable the SPI DMA mode for SPI instances
that enable dma channels in their device tree node.
@ -23,6 +24,7 @@ config SPI_MCUX_LPSPI_DMA
config SPI_MCUX_LPSPI_NORMAL
bool "NXP MCUX LPSPI driver"
default y
depends on $(dt_compat_any_not_has_prop,$(DT_COMPAT_NXP_LPSPI),dmas) || !SPI_MCUX_LPSPI_DMA
help
Use the traditional (non-RTIO) SPI driver for NXP LPSPI.
endif # !SPI_RTIO

387
drivers/spi/spi_nxp_lpspi/spi_mcux_lpspi.c
View file

@ -61,312 +61,6 @@ static void spi_mcux_master_callback(LPSPI_Type *base, lpspi_master_handle_t *ha
spi_mcux_transfer_next_packet(data->dev);
}
/* These flags are arbitrary */
#define LPSPI_DMA_ERROR_FLAG BIT(0)
#define LPSPI_DMA_RX_DONE_FLAG BIT(1)
#define LPSPI_DMA_TX_DONE_FLAG BIT(2)
#define LPSPI_DMA_DONE_FLAG (LPSPI_DMA_RX_DONE_FLAG | LPSPI_DMA_TX_DONE_FLAG)
#ifdef CONFIG_SPI_MCUX_LPSPI_DMA
static bool lpspi_inst_has_dma(const struct spi_mcux_data *data)
{
return (data->dma_tx.dma_dev && data->dma_rx.dma_dev);
}
/* This function is executed in the interrupt context */
static void spi_mcux_dma_callback(const struct device *dev, void *arg, uint32_t channel, int status)
{
/* arg directly holds the spi device */
const struct device *spi_dev = arg;
struct spi_mcux_data *data = (struct spi_mcux_data *)spi_dev->data;
char debug_char;
if (status < 0) {
goto error;
}
/* identify the origin of this callback */
if (channel == data->dma_tx.channel) {
/* this part of the transfer ends */
data->status_flags |= LPSPI_DMA_TX_DONE_FLAG;
debug_char = 'T';
} else if (channel == data->dma_rx.channel) {
/* this part of the transfer ends */
data->status_flags |= LPSPI_DMA_RX_DONE_FLAG;
debug_char = 'R';
} else {
goto error;
}
LOG_DBG("DMA %cX Block Complete", debug_char);
#if CONFIG_SPI_ASYNC
if (data->ctx.asynchronous && (data->status_flags & LPSPI_DMA_DONE_FLAG)) {
/* Load dma blocks of equal length */
size_t dma_size = spi_context_max_continuous_chunk(data->ctx);
if (dma_size != 0) {
return;
}
spi_context_update_tx(&data->ctx, 1, dma_size);
spi_context_update_rx(&data->ctx, 1, dma_size);
}
#endif
goto done;
error:
LOG_ERR("DMA callback error with channel %d.", channel);
data->status_flags |= LPSPI_DMA_ERROR_FLAG;
done:
spi_context_complete(&data->ctx, spi_dev, 0);
}
static struct dma_block_config *spi_mcux_dma_common_load(struct spi_dma_stream *stream,
const struct device *dev,
const uint8_t *buf, size_t len)
{
struct spi_mcux_data *data = dev->data;
struct dma_block_config *blk_cfg = &stream->dma_blk_cfg;
/* prepare the block for this TX DMA channel */
memset(blk_cfg, 0, sizeof(struct dma_block_config));
blk_cfg->block_size = len;
if (buf == NULL) {
blk_cfg->source_address = (uint32_t)&data->dummy_buffer;
blk_cfg->dest_address = (uint32_t)&data->dummy_buffer;
/* pretend it is peripheral xfer so DMA just xfer to dummy buf */
stream->dma_cfg.channel_direction = PERIPHERAL_TO_PERIPHERAL;
} else {
blk_cfg->source_address = (uint32_t)buf;
blk_cfg->dest_address = (uint32_t)buf;
}
/* Transfer 1 byte each DMA loop */
stream->dma_cfg.source_burst_length = 1;
stream->dma_cfg.user_data = (void *)dev;
stream->dma_cfg.head_block = blk_cfg;
return blk_cfg;
}
static int spi_mcux_dma_tx_load(const struct device *dev, const uint8_t *buf, size_t len)
{
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
struct spi_mcux_data *data = dev->data;
/* remember active TX DMA channel (used in callback) */
struct spi_dma_stream *stream = &data->dma_tx;
struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len);
if (buf != NULL) {
/* tx direction has memory as source and periph as dest. */
stream->dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
}
/* Dest is LPSPI tx fifo */
blk_cfg->dest_address = LPSPI_GetTxRegisterAddress(base);
/* give the client dev as arg, as the callback comes from the dma */
/* pass our client origin to the dma: data->dma_tx.dma_channel */
return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
}
static int spi_mcux_dma_rx_load(const struct device *dev, uint8_t *buf, size_t len)
{
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
struct spi_mcux_data *data = dev->data;
/* retrieve active RX DMA channel (used in callback) */
struct spi_dma_stream *stream = &data->dma_rx;
struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len);
if (buf != NULL) {
/* rx direction has periph as source and mem as dest. */
stream->dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
}
/* Source is LPSPI rx fifo */
blk_cfg->source_address = LPSPI_GetRxRegisterAddress(base);
/* pass our client origin to the dma: data->dma_rx.channel */
return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
}
static int wait_dma_rx_tx_done(const struct device *dev)
{
struct spi_mcux_data *data = dev->data;
int ret;
do {
ret = spi_context_wait_for_completion(&data->ctx);
if (ret) {
LOG_DBG("Timed out waiting for SPI context to complete");
return ret;
} else if (data->status_flags & LPSPI_DMA_ERROR_FLAG) {
return -EIO;
}
} while (!((data->status_flags & LPSPI_DMA_DONE_FLAG) == LPSPI_DMA_DONE_FLAG));
LOG_DBG("DMA block completed");
return 0;
}
static inline int spi_mcux_dma_rxtx_load(const struct device *dev, size_t *dma_size)
{
struct spi_mcux_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
int ret = 0;
/* Clear status flags */
data->status_flags = 0U;
/* Load dma blocks of equal length */
*dma_size = spi_context_max_continuous_chunk(ctx);
ret = spi_mcux_dma_tx_load(dev, ctx->tx_buf, *dma_size);
if (ret != 0) {
return ret;
}
ret = spi_mcux_dma_rx_load(dev, ctx->rx_buf, *dma_size);
if (ret != 0) {
return ret;
}
/* Start DMA */
ret = dma_start(data->dma_tx.dma_dev, data->dma_tx.channel);
if (ret != 0) {
return ret;
}
ret = dma_start(data->dma_rx.dma_dev, data->dma_rx.channel);
return ret;
}
#ifdef CONFIG_SPI_ASYNC
static int transceive_dma_async(const struct device *dev, spi_callback_t cb, void *userdata)
{
struct spi_mcux_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
size_t dma_size;
int ret;
ctx->asynchronous = true;
ctx->callback = cb;
ctx->callback_data = userdata;
ret = spi_mcux_dma_rxtx_load(dev, &dma_size);
if (ret) {
return ret;
}
/* Enable DMA Requests */
LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
return 0;
}
#else
#define transceive_dma_async(...) 0
#endif /* CONFIG_SPI_ASYNC */
static int transceive_dma_sync(const struct device *dev)
{
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
struct spi_mcux_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
size_t dma_size;
int ret;
spi_context_cs_control(ctx, true);
/* Send each spi buf via DMA, updating context as DMA completes */
while (ctx->rx_len > 0 || ctx->tx_len > 0) {
/* Load dma block */
ret = spi_mcux_dma_rxtx_load(dev, &dma_size);
if (ret) {
return ret;
}
#ifdef CONFIG_SOC_SERIES_MCXN
while (!(LPSPI_GetStatusFlags(base) & kLPSPI_TxDataRequestFlag)) {
/* wait until previous tx finished */
}
#endif
/* Enable DMA Requests */
LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
/* Wait for DMA to finish */
ret = wait_dma_rx_tx_done(dev);
if (ret) {
return ret;
}
#ifndef CONFIG_SOC_SERIES_MCXN
while ((LPSPI_GetStatusFlags(base) & kLPSPI_ModuleBusyFlag)) {
/* wait until module is idle */
}
#endif
/* Disable DMA */
LPSPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
/* Update SPI contexts with amount of data we just sent */
spi_context_update_tx(ctx, 1, dma_size);
spi_context_update_rx(ctx, 1, dma_size);
}
spi_context_cs_control(ctx, false);
base->TCR = 0;
return 0;
}
static int transceive_dma(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
bool asynchronous, spi_callback_t cb, void *userdata)
{
struct spi_mcux_data *data = dev->data;
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
int ret;
if (!asynchronous) {
spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
}
ret = spi_mcux_configure(dev, spi_cfg);
if (ret && !asynchronous) {
goto out;
} else if (ret) {
return ret;
}
#ifdef CONFIG_SOC_SERIES_MCXN
base->TCR |= LPSPI_TCR_CONT_MASK;
#endif
/* DMA is fast enough watermarks are not required */
LPSPI_SetFifoWatermarks(base, 0U, 0U);
spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
if (asynchronous) {
ret = transceive_dma_async(dev, cb, userdata);
} else {
ret = transceive_dma_sync(dev);
}
out:
spi_context_release(&data->ctx, ret);
return ret;
}
#else
#define lpspi_inst_has_dma(arg) arg != arg
#define transceive_dma(...) 0
#endif /* CONFIG_SPI_MCUX_LPSPI_DMA */
static int transceive(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
bool asynchronous, spi_callback_t cb, void *userdata)
@ -400,24 +94,11 @@ out:
return ret;
}
static int spi_mcux_transceive(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
spi_callback_t cb, void *userdata, bool async)
{
struct spi_mcux_data *data = dev->data;
if (lpspi_inst_has_dma(data)) {
return transceive_dma(dev, spi_cfg, tx_bufs, rx_bufs, async, cb, userdata);
}
return transceive(dev, spi_cfg, tx_bufs, rx_bufs, async, cb, userdata);
}
static int spi_mcux_transceive_sync(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
return spi_mcux_transceive(dev, spi_cfg, tx_bufs, rx_bufs, NULL, NULL, false);
return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
}
#ifdef CONFIG_SPI_ASYNC
@ -426,7 +107,7 @@ static int spi_mcux_transceive_async(const struct device *dev, const struct spi_
const struct spi_buf_set *rx_bufs, spi_callback_t cb,
void *userdata)
{
return spi_mcux_transceive(dev, spi_cfg, tx_bufs, rx_bufs, cb, userdata, true);
return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
}
#endif /* CONFIG_SPI_ASYNC */
@ -438,38 +119,11 @@ static DEVICE_API(spi, spi_mcux_driver_api) = {
.release = spi_mcux_release,
};
#if defined(CONFIG_SPI_MCUX_LPSPI_DMA)
static int lpspi_dma_dev_ready(const struct device *dma_dev)
{
if (!device_is_ready(dma_dev)) {
LOG_ERR("%s device is not ready", dma_dev->name);
return -ENODEV;
}
return 0;
}
static int lpspi_dma_devs_ready(struct spi_mcux_data *data)
{
return lpspi_dma_dev_ready(data->dma_tx.dma_dev) |
lpspi_dma_dev_ready(data->dma_rx.dma_dev);
}
#else
#define lpspi_dma_devs_ready(...) 0
#endif /* CONFIG_SPI_MCUX_LPSPI_DMA */
static int spi_mcux_init(const struct device *dev)
{
struct spi_mcux_data *data = dev->data;
int err = 0;
if (IS_ENABLED(CONFIG_SPI_MCUX_LPSPI_DMA) && lpspi_inst_has_dma(data)) {
err = lpspi_dma_devs_ready(data);
}
if (err < 0) {
return err;
}
err = spi_nxp_init_common(dev);
if (err) {
return err;
@ -480,41 +134,20 @@ static int spi_mcux_init(const struct device *dev)
return 0;
}
#ifdef CONFIG_SPI_MCUX_LPSPI_DMA
#define SPI_DMA_CHANNELS(n) \
IF_ENABLED( \
DT_INST_DMAS_HAS_NAME(n, tx), \
(.dma_tx = {.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, tx)), \
.channel = DT_INST_DMAS_CELL_BY_NAME(n, tx, mux), \
.dma_cfg = {.channel_direction = MEMORY_TO_PERIPHERAL, \
.dma_callback = spi_mcux_dma_callback, \
.source_data_size = 1, \
.dest_data_size = 1, \
.block_count = 1, \
.dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, tx, source)}},)) \
IF_ENABLED( \
DT_INST_DMAS_HAS_NAME(n, rx), \
(.dma_rx = {.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, rx)), \
.channel = DT_INST_DMAS_CELL_BY_NAME(n, rx, mux), \
.dma_cfg = {.channel_direction = PERIPHERAL_TO_MEMORY, \
.dma_callback = spi_mcux_dma_callback, \
.source_data_size = 1, \
.dest_data_size = 1, \
.block_count = 1, \
.dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, rx, source)}},))
#else
#define SPI_DMA_CHANNELS(n)
#endif /* CONFIG_SPI_MCUX_LPSPI_DMA */
#define SPI_MCUX_LPSPI_INIT(n) \
#define LPSPI_INIT(n) \
SPI_NXP_LPSPI_COMMON_INIT(n) \
SPI_MCUX_LPSPI_CONFIG_INIT(n) \
\
static struct spi_mcux_data spi_mcux_data_##n = {SPI_NXP_LPSPI_COMMON_DATA_INIT(n) \
SPI_DMA_CHANNELS(n)}; \
static struct spi_mcux_data spi_mcux_data_##n = {SPI_NXP_LPSPI_COMMON_DATA_INIT(n)}; \
\
SPI_DEVICE_DT_INST_DEFINE(n, spi_mcux_init, NULL, &spi_mcux_data_##n, \
&spi_mcux_config_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_mcux_driver_api);
#define SPI_MCUX_LPSPI_INIT_IF_DMA(n) IF_DISABLED(SPI_NXP_LPSPI_HAS_DMAS(n), (LPSPI_INIT(n)))
#define SPI_MCUX_LPSPI_INIT(n) \
COND_CODE_1(CONFIG_SPI_MCUX_LPSPI_DMA, \
(SPI_MCUX_LPSPI_INIT_IF_DMA(n)), (LPSPI_INIT(n)))
DT_INST_FOREACH_STATUS_OKAY(SPI_MCUX_LPSPI_INIT)

411
drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_dma.c Normal file
View file

@ -0,0 +1,411 @@
/*
* Copyright 2018, 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpspi
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_mcux_lpspi_dma, CONFIG_SPI_LOG_LEVEL);
#include "spi_nxp_lpspi_priv.h"
/* These flags are arbitrary */
#define LPSPI_DMA_ERROR_FLAG BIT(0)
#define LPSPI_DMA_RX_DONE_FLAG BIT(1)
#define LPSPI_DMA_TX_DONE_FLAG BIT(2)
#define LPSPI_DMA_DONE_FLAG (LPSPI_DMA_RX_DONE_FLAG | LPSPI_DMA_TX_DONE_FLAG)
/* This function is executed in the interrupt context */
static void spi_mcux_dma_callback(const struct device *dev, void *arg, uint32_t channel, int status)
{
/* arg directly holds the spi device */
const struct device *spi_dev = arg;
struct spi_mcux_data *data = (struct spi_mcux_data *)spi_dev->data;
char debug_char;
if (status < 0) {
goto error;
}
/* identify the origin of this callback */
if (channel == data->dma_tx.channel) {
/* this part of the transfer ends */
data->status_flags |= LPSPI_DMA_TX_DONE_FLAG;
debug_char = 'T';
} else if (channel == data->dma_rx.channel) {
/* this part of the transfer ends */
data->status_flags |= LPSPI_DMA_RX_DONE_FLAG;
debug_char = 'R';
} else {
goto error;
}
LOG_DBG("DMA %cX Block Complete", debug_char);
#if CONFIG_SPI_ASYNC
if (data->ctx.asynchronous && (data->status_flags & LPSPI_DMA_DONE_FLAG)) {
/* Load dma blocks of equal length */
size_t dma_size = spi_context_max_continuous_chunk(data->ctx);
if (dma_size != 0) {
return;
}
spi_context_update_tx(&data->ctx, 1, dma_size);
spi_context_update_rx(&data->ctx, 1, dma_size);
}
#endif
goto done;
error:
LOG_ERR("DMA callback error with channel %d.", channel);
data->status_flags |= LPSPI_DMA_ERROR_FLAG;
done:
spi_context_complete(&data->ctx, spi_dev, 0);
}
static struct dma_block_config *spi_mcux_dma_common_load(struct spi_dma_stream *stream,
const struct device *dev,
const uint8_t *buf, size_t len)
{
struct spi_mcux_data *data = dev->data;
struct dma_block_config *blk_cfg = &stream->dma_blk_cfg;
/* prepare the block for this TX DMA channel */
memset(blk_cfg, 0, sizeof(struct dma_block_config));
blk_cfg->block_size = len;
if (buf == NULL) {
blk_cfg->source_address = (uint32_t)&data->dummy_buffer;
blk_cfg->dest_address = (uint32_t)&data->dummy_buffer;
/* pretend it is peripheral xfer so DMA just xfer to dummy buf */
stream->dma_cfg.channel_direction = PERIPHERAL_TO_PERIPHERAL;
} else {
blk_cfg->source_address = (uint32_t)buf;
blk_cfg->dest_address = (uint32_t)buf;
}
/* Transfer 1 byte each DMA loop */
stream->dma_cfg.source_burst_length = 1;
stream->dma_cfg.user_data = (void *)dev;
stream->dma_cfg.head_block = blk_cfg;
return blk_cfg;
}
static int spi_mcux_dma_tx_load(const struct device *dev, const uint8_t *buf, size_t len)
{
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
struct spi_mcux_data *data = dev->data;
/* remember active TX DMA channel (used in callback) */
struct spi_dma_stream *stream = &data->dma_tx;
struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len);
if (buf != NULL) {
/* tx direction has memory as source and periph as dest. */
stream->dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
}
/* Dest is LPSPI tx fifo */
blk_cfg->dest_address = LPSPI_GetTxRegisterAddress(base);
/* give the client dev as arg, as the callback comes from the dma */
/* pass our client origin to the dma: data->dma_tx.dma_channel */
return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
}
static int spi_mcux_dma_rx_load(const struct device *dev, uint8_t *buf, size_t len)
{
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
struct spi_mcux_data *data = dev->data;
/* retrieve active RX DMA channel (used in callback) */
struct spi_dma_stream *stream = &data->dma_rx;
struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len);
if (buf != NULL) {
/* rx direction has periph as source and mem as dest. */
stream->dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
}
/* Source is LPSPI rx fifo */
blk_cfg->source_address = LPSPI_GetRxRegisterAddress(base);
/* pass our client origin to the dma: data->dma_rx.channel */
return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
}
static int wait_dma_rx_tx_done(const struct device *dev)
{
struct spi_mcux_data *data = dev->data;
int ret;
do {
ret = spi_context_wait_for_completion(&data->ctx);
if (ret) {
LOG_DBG("Timed out waiting for SPI context to complete");
return ret;
} else if (data->status_flags & LPSPI_DMA_ERROR_FLAG) {
return -EIO;
}
} while (!((data->status_flags & LPSPI_DMA_DONE_FLAG) == LPSPI_DMA_DONE_FLAG));
LOG_DBG("DMA block completed");
return 0;
}
static inline int spi_mcux_dma_rxtx_load(const struct device *dev, size_t *dma_size)
{
struct spi_mcux_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
int ret = 0;
/* Clear status flags */
data->status_flags = 0U;
/* Load dma blocks of equal length */
*dma_size = spi_context_max_continuous_chunk(ctx);
ret = spi_mcux_dma_tx_load(dev, ctx->tx_buf, *dma_size);
if (ret != 0) {
return ret;
}
ret = spi_mcux_dma_rx_load(dev, ctx->rx_buf, *dma_size);
if (ret != 0) {
return ret;
}
/* Start DMA */
ret = dma_start(data->dma_tx.dma_dev, data->dma_tx.channel);
if (ret != 0) {
return ret;
}
ret = dma_start(data->dma_rx.dma_dev, data->dma_rx.channel);
return ret;
}
#ifdef CONFIG_SPI_ASYNC
static int transceive_dma_async(const struct device *dev, spi_callback_t cb, void *userdata)
{
struct spi_mcux_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
size_t dma_size;
int ret;
ctx->asynchronous = true;
ctx->callback = cb;
ctx->callback_data = userdata;
ret = spi_mcux_dma_rxtx_load(dev, &dma_size);
if (ret) {
return ret;
}
/* Enable DMA Requests */
LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
return 0;
}
#else
#define transceive_dma_async(...) 0
#endif /* CONFIG_SPI_ASYNC */
static int transceive_dma_sync(const struct device *dev)
{
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
struct spi_mcux_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
size_t dma_size;
int ret;
spi_context_cs_control(ctx, true);
/* Send each spi buf via DMA, updating context as DMA completes */
while (ctx->rx_len > 0 || ctx->tx_len > 0) {
/* Load dma block */
ret = spi_mcux_dma_rxtx_load(dev, &dma_size);
if (ret) {
return ret;
}
#ifdef CONFIG_SOC_SERIES_MCXN
while (!(LPSPI_GetStatusFlags(base) & kLPSPI_TxDataRequestFlag)) {
/* wait until previous tx finished */
}
#endif
/* Enable DMA Requests */
LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
/* Wait for DMA to finish */
ret = wait_dma_rx_tx_done(dev);
if (ret) {
return ret;
}
#ifndef CONFIG_SOC_SERIES_MCXN
while ((LPSPI_GetStatusFlags(base) & kLPSPI_ModuleBusyFlag)) {
/* wait until module is idle */
}
#endif
/* Disable DMA */
LPSPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
/* Update SPI contexts with amount of data we just sent */
spi_context_update_tx(ctx, 1, dma_size);
spi_context_update_rx(ctx, 1, dma_size);
}
spi_context_cs_control(ctx, false);
base->TCR = 0;
return 0;
}
static int transceive_dma(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
bool asynchronous, spi_callback_t cb, void *userdata)
{
struct spi_mcux_data *data = dev->data;
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
int ret;
if (!asynchronous) {
spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
}
ret = spi_mcux_configure(dev, spi_cfg);
if (ret && !asynchronous) {
goto out;
} else if (ret) {
return ret;
}
#ifdef CONFIG_SOC_SERIES_MCXN
base->TCR |= LPSPI_TCR_CONT_MASK;
#endif
/* DMA is fast enough watermarks are not required */
LPSPI_SetFifoWatermarks(base, 0U, 0U);
spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
if (asynchronous) {
ret = transceive_dma_async(dev, cb, userdata);
} else {
ret = transceive_dma_sync(dev);
}
out:
spi_context_release(&data->ctx, ret);
return ret;
}
static int lpspi_dma_dev_ready(const struct device *dma_dev)
{
if (!device_is_ready(dma_dev)) {
LOG_ERR("%s device is not ready", dma_dev->name);
return -ENODEV;
}
return 0;
}
static int lpspi_dma_devs_ready(struct spi_mcux_data *data)
{
return lpspi_dma_dev_ready(data->dma_tx.dma_dev) |
lpspi_dma_dev_ready(data->dma_rx.dma_dev);
}
static int spi_mcux_dma_init(const struct device *dev)
{
struct spi_mcux_data *data = dev->data;
int err = 0;
err = lpspi_dma_devs_ready(data);
if (err < 0) {
return err;
}
err = spi_nxp_init_common(dev);
if (err) {
return err;
}
spi_context_unlock_unconditionally(&data->ctx);
return 0;
}
static int spi_nxp_dma_transceive_sync(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
return transceive_dma(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
}
#ifdef CONFIG_SPI_ASYNC
static int spi_nxp_dma_transceive_async(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs, spi_callback_t cb,
void *userdata)
{
return transceive_dma(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
}
#endif /* CONFIG_SPI_ASYNC */
static DEVICE_API(spi, spi_mcux_driver_api) = {
.transceive = spi_nxp_dma_transceive_sync,
#ifdef CONFIG_SPI_ASYNC
.transceive_async = spi_nxp_dma_transceive_async,
#endif
.release = spi_mcux_release,
};
static void lpspi_isr(const struct device *dev)
{
/* ISR not used for DMA based LPSPI driver */
}
#define SPI_DMA_CHANNELS(n) \
IF_ENABLED( \
DT_INST_DMAS_HAS_NAME(n, tx), \
(.dma_tx = {.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, tx)), \
.channel = DT_INST_DMAS_CELL_BY_NAME(n, tx, mux), \
.dma_cfg = {.channel_direction = MEMORY_TO_PERIPHERAL, \
.dma_callback = spi_mcux_dma_callback, \
.source_data_size = 1, \
.dest_data_size = 1, \
.block_count = 1, \
.dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, tx, source)}},)) \
IF_ENABLED( \
DT_INST_DMAS_HAS_NAME(n, rx), \
(.dma_rx = {.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, rx)), \
.channel = DT_INST_DMAS_CELL_BY_NAME(n, rx, mux), \
.dma_cfg = {.channel_direction = PERIPHERAL_TO_MEMORY, \
.dma_callback = spi_mcux_dma_callback, \
.source_data_size = 1, \
.dest_data_size = 1, \
.block_count = 1, \
.dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, rx, source)}},))
#define LPSPI_DMA_INIT(n) \
SPI_NXP_LPSPI_COMMON_INIT(n) \
SPI_MCUX_LPSPI_CONFIG_INIT(n) \
\
static struct spi_mcux_data spi_mcux_data_##n = {SPI_NXP_LPSPI_COMMON_DATA_INIT(n) \
SPI_DMA_CHANNELS(n)}; \
\
SPI_DEVICE_DT_INST_DEFINE(n, spi_mcux_dma_init, NULL, &spi_mcux_data_##n, \
&spi_mcux_config_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_mcux_driver_api);
#define SPI_NXP_LPSPI_DMA_INIT(n) IF_ENABLED(SPI_NXP_LPSPI_HAS_DMAS(n), (LPSPI_DMA_INIT(n)))
DT_INST_FOREACH_STATUS_OKAY(SPI_NXP_LPSPI_DMA_INIT)

3
drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_priv.h
View file

@ -129,3 +129,6 @@ int spi_mcux_release(const struct device *dev, const struct spi_config *spi_cfg)
SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##n, ctx), \
SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##n, ctx), \
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)
#define SPI_NXP_LPSPI_HAS_DMAS(n) \
UTIL_AND(DT_INST_DMAS_HAS_NAME(n, tx), DT_INST_DMAS_HAS_NAME(n, rx))