intel_adsp: ace: rename namespace: MTL -> ACE
MTL is just one platform and this code is going to be used in multiple platforms currently under development, so reduce the confusion and move to a common namespace. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
parent
0869e62539
commit
6c3277eada
3 changed files with 15 additions and 15 deletions
|
@ -186,7 +186,7 @@ static uint16_t tlb_perms_to_flags(uint16_t perms)
|
||||||
static int sys_mm_drv_hpsram_pwr(uint32_t bank_idx, bool enable, bool non_blocking)
|
static int sys_mm_drv_hpsram_pwr(uint32_t bank_idx, bool enable, bool non_blocking)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
|
#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
|
||||||
if (bank_idx > mtl_hpsram_get_bank_count()) {
|
if (bank_idx > ace_hpsram_get_bank_count()) {
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -63,7 +63,7 @@
|
||||||
/* These registers are for the L2 memory control and status. */
|
/* These registers are for the L2 memory control and status. */
|
||||||
#define DFL2MM_REG 0x71d00
|
#define DFL2MM_REG 0x71d00
|
||||||
|
|
||||||
struct mtl_l2mm {
|
struct ace_l2mm {
|
||||||
uint32_t l2mcap;
|
uint32_t l2mcap;
|
||||||
uint32_t l2mpat;
|
uint32_t l2mpat;
|
||||||
uint32_t l2mecap;
|
uint32_t l2mecap;
|
||||||
|
@ -75,10 +75,10 @@ struct mtl_l2mm {
|
||||||
uint32_t l2ucmrpdptr;
|
uint32_t l2ucmrpdptr;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define MTL_L2MM ((volatile struct mtl_l2mm *)DFL2MM_REG)
|
#define ACE_L2MM ((volatile struct ace_l2mm *)DFL2MM_REG)
|
||||||
|
|
||||||
/* DfL2MCAP */
|
/* DfL2MCAP */
|
||||||
struct mtl_l2mcap {
|
struct ace_l2mcap {
|
||||||
uint32_t l2hss : 8;
|
uint32_t l2hss : 8;
|
||||||
uint32_t l2uss : 4;
|
uint32_t l2uss : 4;
|
||||||
uint32_t l2hsbs : 4;
|
uint32_t l2hsbs : 4;
|
||||||
|
@ -89,19 +89,19 @@ struct mtl_l2mcap {
|
||||||
uint32_t rsvd32 : 1;
|
uint32_t rsvd32 : 1;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define MTL_L2MCAP ((volatile struct mtl_l2mcap *)DFL2MM_REG)
|
#define ACE_L2MCAP ((volatile struct ace_l2mcap *)DFL2MM_REG)
|
||||||
|
|
||||||
static inline uint32_t mtl_hpsram_get_bank_count(void)
|
static inline uint32_t ace_hpsram_get_bank_count(void)
|
||||||
{
|
{
|
||||||
return MTL_L2MCAP->l2hss;
|
return ACE_L2MCAP->l2hss;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline uint32_t mtl_lpsram_get_bank_count(void)
|
static inline uint32_t ace_lpsram_get_bank_count(void)
|
||||||
{
|
{
|
||||||
return MTL_L2MCAP->l2uss;
|
return ACE_L2MCAP->l2uss;
|
||||||
}
|
}
|
||||||
|
|
||||||
struct mtl_hpsram_regs {
|
struct ace_hpsram_regs {
|
||||||
/** @brief power gating control */
|
/** @brief power gating control */
|
||||||
uint8_t HSxPGCTL;
|
uint8_t HSxPGCTL;
|
||||||
/** @brief retention mode control */
|
/** @brief retention mode control */
|
||||||
|
@ -117,7 +117,7 @@ struct mtl_hpsram_regs {
|
||||||
#define L2HSBPM_REG 0x17A800
|
#define L2HSBPM_REG 0x17A800
|
||||||
#define L2HSBPM_REG_SIZE 0x0008
|
#define L2HSBPM_REG_SIZE 0x0008
|
||||||
|
|
||||||
#define HPSRAM_REGS(block_idx) ((volatile struct mtl_hpsram_regs *const) \
|
#define HPSRAM_REGS(block_idx) ((volatile struct ace_hpsram_regs *const) \
|
||||||
(L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx)))
|
(L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx)))
|
||||||
|
|
||||||
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
|
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
|
||||||
|
|
|
@ -19,8 +19,8 @@ __imr void hp_sram_init(uint32_t memory_size)
|
||||||
{
|
{
|
||||||
ARG_UNUSED(memory_size);
|
ARG_UNUSED(memory_size);
|
||||||
|
|
||||||
uint32_t hpsram_ebb_quantity = mtl_hpsram_get_bank_count();
|
uint32_t hpsram_ebb_quantity = ace_hpsram_get_bank_count();
|
||||||
volatile uint32_t *l2hsbpmptr = (volatile uint32_t *)MTL_L2MM->l2hsbpmptr;
|
volatile uint32_t *l2hsbpmptr = (volatile uint32_t *)ACE_L2MM->l2hsbpmptr;
|
||||||
volatile uint8_t *status = (volatile uint8_t *)l2hsbpmptr + 4;
|
volatile uint8_t *status = (volatile uint8_t *)l2hsbpmptr + 4;
|
||||||
int idx;
|
int idx;
|
||||||
|
|
||||||
|
@ -36,8 +36,8 @@ __imr void hp_sram_init(uint32_t memory_size)
|
||||||
|
|
||||||
__imr void lp_sram_init(void)
|
__imr void lp_sram_init(void)
|
||||||
{
|
{
|
||||||
uint32_t lpsram_ebb_quantity = mtl_lpsram_get_bank_count();
|
uint32_t lpsram_ebb_quantity = ace_lpsram_get_bank_count();
|
||||||
volatile uint32_t *l2usbpmptr = (volatile uint32_t *)MTL_L2MM->l2usbpmptr;
|
volatile uint32_t *l2usbpmptr = (volatile uint32_t *)ACE_L2MM->l2usbpmptr;
|
||||||
|
|
||||||
for (uint32_t idx = 0; idx < lpsram_ebb_quantity; ++idx) {
|
for (uint32_t idx = 0; idx < lpsram_ebb_quantity; ++idx) {
|
||||||
*(l2usbpmptr + idx * 2) = 0;
|
*(l2usbpmptr + idx * 2) = 0;
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue