soc: arm: stm32wba: add support for standby mode with ram retention
Add support for STM32WBA Standby low-power mode with RAM retention. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
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624139ad9a
commit
6b681bcbcc
4 changed files with 131 additions and 23 deletions
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@ -39,4 +39,26 @@ config ENTROPY_STM32_CLK_CHECK
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endif
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if PM_S2RAM
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config COUNTER
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default y
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config COUNTER_RTC_STM32_SUBSECONDS
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default y
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config STM32_LPTIM_STDBY_TIMER
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default y
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config TICKLESS_KERNEL
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default y
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config COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS
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default y
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config IDLE_STACK_SIZE
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default 512
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endif
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endif # SOC_SERIES_STM32WBAX
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@ -7,6 +7,8 @@
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#include <zephyr/pm/pm.h>
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#include <soc.h>
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#include <zephyr/init.h>
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#include <zephyr/arch/common/pm_s2ram.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <stm32wbaxx_ll_bus.h>
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#include <stm32wbaxx_ll_cortex.h>
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@ -24,7 +26,25 @@
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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void set_mode_stop(uint8_t substate_id)
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static int stm32_power_init(void);
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static void disable_cache(void)
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{
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/* Disabling ICACHE */
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LL_ICACHE_Disable();
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while (LL_ICACHE_IsEnabled() == 1U) {
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}
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/* Wait until ICACHE_SR.BUSYF is cleared */
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while (LL_ICACHE_IsActiveFlag_BUSY() == 1U) {
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}
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/* Wait until ICACHE_SR.BSYENDF is set */
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while (LL_ICACHE_IsActiveFlag_BSYEND() == 0U) {
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}
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}
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static void set_mode_stop(uint8_t substate_id)
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{
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LL_PWR_ClearFlag_STOP();
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@ -33,10 +53,7 @@ void set_mode_stop(uint8_t substate_id)
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/* Erratum 2.2.15:
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* Disabling ICACHE is required before entering stop mode
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*/
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LL_ICACHE_Disable();
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while (LL_ICACHE_IsEnabled() == 1U) {
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}
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disable_cache();
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#ifdef CONFIG_BT_STM32WBA
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scm_setwaitstates(LP);
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@ -60,35 +77,76 @@ void set_mode_stop(uint8_t substate_id)
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}
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}
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#if defined(CONFIG_PM_S2RAM)
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static int suspend_to_ram(void)
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{
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LL_LPM_EnableDeepSleep();
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while (LL_PWR_IsActiveFlag_ACTVOS() == 0) {
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}
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/* Select mode entry : WFE or WFI and enter the CPU selected mode */
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k_cpu_idle();
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return 0;
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}
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static void set_mode_suspend_to_ram(void)
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{
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/* Enable SRAM full retention */
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LL_PWR_SetSRAM1SBRetention(LL_PWR_SRAM1_SB_FULL_RETENTION);
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LL_PWR_SetSRAM2SBRetention(LL_PWR_SRAM2_SB_FULL_RETENTION);
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/* Enable RTC wakeup
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* This configures an internal pin that generates an event to wakeup the system
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*/
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LL_PWR_EnableWakeUpPin(LL_PWR_WAKEUP_PIN7);
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LL_PWR_SetWakeUpPinSignal3Selection(LL_PWR_WAKEUP_PIN7);
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/* Clear flags */
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LL_PWR_ClearFlag_SB();
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LL_PWR_ClearFlag_WU();
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LL_RCC_ClearResetFlags();
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disable_cache();
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/* Select standby mode */
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LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
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/* Save context and enter Standby mode */
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arch_pm_s2ram_suspend(suspend_to_ram);
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/* Execution is restored at this point after wake up */
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/* Restore system clock as soon as we exit standby mode */
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sys_clock_idle_exit();
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}
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#endif
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/* Invoke Low Power/System Off specific Tasks */
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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set_mode_stop(substate_id);
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/* Select mode entry : WFE or WFI and enter the CPU selected mode */
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k_cpu_idle();
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break;
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case PM_STATE_STANDBY:
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/* Not supported today */
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__fallthrough;
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#if defined(CONFIG_PM_S2RAM)
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case PM_STATE_SUSPEND_TO_RAM:
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set_mode_suspend_to_ram();
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break;
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#endif
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default:
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LOG_DBG("Unsupported power state %u", state);
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return;
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}
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/* Select mode entry : WFE or WFI and enter the CPU selected mode */
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k_cpu_idle();
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}
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/* Handle SOC specific activity after Low Power Mode Exit */
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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/* Erratum 2.2.15:
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* Enable ICACHE when exiting stop mode
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*/
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LL_ICACHE_Enable();
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while (LL_ICACHE_IsEnabled() == 0U) {
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}
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#ifdef CONFIG_BT_STM32WBA
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if (LL_PWR_IsActiveFlag_STOP() == 1U) {
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scm_setup();
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@ -100,16 +158,33 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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if (substate_id <= 2) {
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/* Erratum 2.2.15:
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* Enable ICACHE when exiting stop mode
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*/
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LL_ICACHE_SetMode(LL_ICACHE_1WAY);
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LL_ICACHE_Enable();
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while (LL_ICACHE_IsEnabled() == 0U) {
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}
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LL_LPM_DisableSleepOnExit();
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LL_LPM_EnableSleep();
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} else {
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LOG_DBG("Unsupported power substate-id %u",
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substate_id);
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}
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case PM_STATE_STANDBY:
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/* To be tested */
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LL_LPM_EnableSleep();
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break;
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case PM_STATE_SUSPEND_TO_RAM:
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#if defined(CONFIG_PM_S2RAM)
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stm32wba_init();
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stm32_power_init();
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LL_LPM_DisableSleepOnExit();
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LL_LPM_EnableSleep();
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#else
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LOG_DBG("Suspend to RAM needs CONFIG_PM_S2RAM to be enabled");
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#endif
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break;
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case PM_STATE_STANDBY:
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__fallthrough;
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case PM_STATE_SUSPEND_TO_DISK:
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__fallthrough;
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@ -141,6 +216,15 @@ static int stm32_power_init(void)
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
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#ifdef CONFIG_DEBUG
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LL_DBGMCU_EnableDBGStandbyMode();
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LL_DBGMCU_APB7_GRP1_FreezePeriph(LL_DBGMCU_APB7_GRP1_RTC_STOP);
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LL_DBGMCU_APB7_GRP1_FreezePeriph(LL_DBGMCU_APB7_GRP1_LPTIM1_STOP);
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#else
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LL_DBGMCU_DisableDBGStandbyMode();
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#endif
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/* Enabling Ultra Low power mode */
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LL_PWR_EnableUltraLowPowerMode();
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LL_FLASH_EnableSleepPowerDown();
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@ -32,7 +32,7 @@ LOG_MODULE_REGISTER(soc);
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*
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* @return 0
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*/
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static int stm32wba_init(void)
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int stm32wba_init(void)
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{
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/* Enable instruction cache in 1-way (direct mapped cache) */
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LL_ICACHE_SetMode(LL_ICACHE_1WAY);
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@ -51,7 +51,6 @@ static int stm32wba_init(void)
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LL_PWR_SetRegulatorSupply(LL_PWR_LDO_SUPPLY);
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#endif
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return 0;
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}
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@ -17,6 +17,9 @@
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#include <stm32wbaxx.h>
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/* function exported to the soc power.c */
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int stm32wba_init(void);
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32WBA_SOC_H_ */
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