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soc: xtensa,riscv: esp32xx: refactor folder structure

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Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej 2023-07-20 18:24:09 +02:00 • committed by Carles Cufí
commit 6b57b3b786
154 changed files with 1049 additions and 1646 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Kconfig.zephyr
View file

@ -594,7 +594,7 @@ if BUILD_OUTPUT_UF2
config BUILD_OUTPUT_UF2_FAMILY_ID config BUILD_OUTPUT_UF2_FAMILY_ID
string "UF2 device family ID" string "UF2 device family ID"
default "0x1c5f21b0" if SOC_ESP32 default "0x1c5f21b0" if SOC_SERIES_ESP32
default "0x621e937a" if SOC_NRF52833_QIAA default "0x621e937a" if SOC_NRF52833_QIAA
default "0xada52840" if SOC_NRF52840_QIAA default "0xada52840" if SOC_NRF52840_QIAA
default "0x4fb2d5bd" if SOC_SERIES_IMX_RT default "0x4fb2d5bd" if SOC_SERIES_IMX_RT

2
arch/xtensa/Kconfig
View file

@ -46,7 +46,7 @@ config XTENSA_USE_CORE_CRT1
config XTENSA_ENABLE_BACKTRACE config XTENSA_ENABLE_BACKTRACE
bool "Backtrace on panic exception" bool "Backtrace on panic exception"
default y default y
depends on SOC_ESP32 || SOC_FAMILY_INTEL_ADSP depends on SOC_SERIES_ESP32 || SOC_FAMILY_INTEL_ADSP
help help
Enable this config option to print backtrace on panic exception Enable this config option to print backtrace on panic exception

8
arch/xtensa/core/coredump.c
View file

@ -109,13 +109,13 @@ void arch_coredump_info_dump(const z_arch_esf_t *esf)
#if CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER #if CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER
arch_blk.soc = XTENSA_SOC_SAMPLE_CONTROLLER; arch_blk.soc = XTENSA_SOC_SAMPLE_CONTROLLER;
#elif CONFIG_SOC_ESP32
arch_blk.soc = XTENSA_SOC_ESP32;
#elif CONFIG_SOC_FAMILY_INTEL_ADSP #elif CONFIG_SOC_FAMILY_INTEL_ADSP
arch_blk.soc = XTENSA_SOC_INTEL_ADSP; arch_blk.soc = XTENSA_SOC_INTEL_ADSP;
#elif CONFIG_SOC_ESP32S2 #elif CONFIG_SOC_SERIES_ESP32
arch_blk.soc = XTENSA_SOC_ESP32;
#elif CONFIG_SOC_SERIES_ESP32S2
arch_blk.soc = XTENSA_SOC_ESP32S2; arch_blk.soc = XTENSA_SOC_ESP32S2;
#elif CONFIG_SOC_ESP32S3 #elif CONFIG_SOC_SERIES_ESP32S3
arch_blk.soc = XTENSA_SOC_ESP32S3; arch_blk.soc = XTENSA_SOC_ESP32S3;
#else #else
arch_blk.soc = XTENSA_SOC_UNKNOWN; arch_blk.soc = XTENSA_SOC_UNKNOWN;

6
arch/xtensa/core/xtensa_backtrace.c
View file

@ -7,7 +7,7 @@
#include "xtensa/corebits.h" #include "xtensa/corebits.h"
#include "xtensa_backtrace.h" #include "xtensa_backtrace.h"
#include <zephyr/sys/printk.h> #include <zephyr/sys/printk.h>
#if defined(CONFIG_SOC_ESP32) #if defined(CONFIG_SOC_SERIES_ESP32)
#include "soc/soc_memory_layout.h" #include "soc/soc_memory_layout.h"
#elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP)
#include "debug_helpers.h" #include "debug_helpers.h"
@ -34,7 +34,7 @@ static inline uint32_t z_xtensa_cpu_process_stack_pc(uint32_t pc)
static inline bool z_xtensa_stack_ptr_is_sane(uint32_t sp) static inline bool z_xtensa_stack_ptr_is_sane(uint32_t sp)
{ {
#if defined(CONFIG_SOC_ESP32) #if defined(CONFIG_SOC_SERIES_ESP32)
return esp_stack_ptr_is_sane(sp); return esp_stack_ptr_is_sane(sp);
#elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP)
return intel_adsp_ptr_is_sane(sp); return intel_adsp_ptr_is_sane(sp);
@ -45,7 +45,7 @@ static inline bool z_xtensa_stack_ptr_is_sane(uint32_t sp)
static inline bool z_xtensa_ptr_executable(const void *p) static inline bool z_xtensa_ptr_executable(const void *p)
{ {
#if defined(CONFIG_SOC_ESP32) #if defined(CONFIG_SOC_SERIES_ESP32)
return esp_ptr_executable(p); return esp_ptr_executable(p);
#elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP)
return intel_adsp_ptr_executable(p); return intel_adsp_ptr_executable(p);

6
boards/riscv/esp32c3_devkitm/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_ESP32C3_DEVKITM config BOARD_ESP32C3_DEVKITM
bool "ESP32C3 Devkit-M Board" bool "ESP32C3 Devkit-M Board"
depends on SOC_ESP32C3 depends on SOC_SERIES_ESP32C3
choice SOC_PART_NUMBER
default SOC_ESP32C3_MINI_N4
endchoice

6
boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig
View file

@ -1,11 +1,11 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_BOARD_ESP32C3_DEVKITM=y CONFIG_BOARD_ESP32C3_DEVKITM=y
CONFIG_SOC_ESP32C3=y CONFIG_SOC_SERIES_ESP32C3=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL=y

6
boards/riscv/icev_wireless/icev_wireless_defconfig
View file

@ -1,11 +1,11 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_BOARD_ICEV_WIRELESS=y CONFIG_BOARD_ICEV_WIRELESS=y
CONFIG_SOC_ESP32C3=y CONFIG_SOC_SERIES_ESP32C3=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL=y

6
boards/riscv/stamp_c3/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_STAMP_C3 config BOARD_STAMP_C3
bool "M5Stack STAMP-C3 Board" bool "M5Stack STAMP-C3 Board"
depends on SOC_ESP32C3 depends on SOC_SERIES_ESP32C3
choice SOC_PART_NUMBER
default SOC_ESP32C3_FX4
endchoice

7
boards/riscv/stamp_c3/stamp_c3_defconfig
View file

@ -1,12 +1,13 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_BOARD_STAMP_C3=y CONFIG_BOARD_STAMP_C3=y
CONFIG_SOC_ESP32C3=y CONFIG_SOC_SERIES_ESP32C3=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000
CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL=y

6
boards/riscv/xiao_esp32c3/Kconfig.board
View file

@ -3,4 +3,8 @@
config BOARD_XIAO_ESP32C3 config BOARD_XIAO_ESP32C3
bool "XIAO ESP32C3 Board" bool "XIAO ESP32C3 Board"
depends on SOC_ESP32C3 depends on SOC_SERIES_ESP32C3
choice SOC_PART_NUMBER
default SOC_ESP32C3_FX4
endchoice

6
boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig
View file

@ -1,11 +1,11 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_BOARD_XIAO_ESP32C3=y CONFIG_BOARD_XIAO_ESP32C3=y
CONFIG_SOC_ESP32C3=y CONFIG_SOC_SERIES_ESP32C3=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/esp32_devkitc_wroom/Kconfig.board
View file

@ -3,4 +3,8 @@
config BOARD_ESP32_DEVKITC_WROOM config BOARD_ESP32_DEVKITC_WROOM
bool "ESP32-DEVKITC-WROOM Development Board" bool "ESP32-DEVKITC-WROOM Development Board"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
choice SOC_PART_NUMBER
default SOC_ESP32_WROOM_32UE_N4
endchoice

11
boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig
View file

@ -1,10 +1,8 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ESP32_DEVKITC_WROOM=y CONFIG_BOARD_ESP32_DEVKITC_WROOM=y
CONFIG_SOC_ESP32=y CONFIG_SOC_SERIES_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
@ -12,11 +10,4 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/esp32_devkitc_wrover/Kconfig.board
View file

@ -3,4 +3,8 @@
config BOARD_ESP32_DEVKITC_WROVER config BOARD_ESP32_DEVKITC_WROVER
bool "ESP32-DEVKITC-WROVER-E Development board" bool "ESP32-DEVKITC-WROVER-E Development board"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
choice SOC_PART_NUMBER
default SOC_ESP32_WROVER_E_N4R8
endchoice

11
boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig
View file

@ -1,10 +1,8 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ESP32_DEVKITC_WROVER=y CONFIG_BOARD_ESP32_DEVKITC_WROVER=y
CONFIG_SOC_ESP32=y CONFIG_SOC_SERIES_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
@ -12,11 +10,4 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/esp32_ethernet_kit/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_ESP32_ETHERNET_KIT config BOARD_ESP32_ETHERNET_KIT
bool "ESP32-ETHERNET-KIT Development Board" bool "ESP32-ETHERNET-KIT Development Board"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
choice SOC_PART_NUMBER
default SOC_ESP32_WROVER_E_N4R8
endchoice

11
boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig
View file

@ -1,9 +1,7 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ESP32_ETHERNET_KIT=y CONFIG_BOARD_ESP32_ETHERNET_KIT=y
CONFIG_SOC_ESP32=y CONFIG_SOC_SERIES_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
@ -11,11 +9,4 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/esp32_net/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_ESP32_NET config BOARD_ESP32_NET
bool "ESP32 Board configuration for APP_CPU" bool "ESP32 Board configuration for APP_CPU"
depends on SOC_ESP32_NET depends on SOC_SERIES_ESP32_NET
choice SOC_PART_NUMBER
default SOC_ESP32_NET
endchoice

10
boards/xtensa/esp32_net/esp32_net_defconfig
View file

@ -1,9 +1,7 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ESP32_NET=y CONFIG_BOARD_ESP32_NET=y
CONFIG_SOC_ESP32_NET=y CONFIG_SOC_SERIES_ESP32_NET=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
@ -11,13 +9,7 @@ CONFIG_CONSOLE=n
CONFIG_SERIAL=n CONFIG_SERIAL=n
CONFIG_UART_CONSOLE=n CONFIG_UART_CONSOLE=n
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=n CONFIG_GPIO=n
CONFIG_GPIO_ESP32=n CONFIG_GPIO_ESP32=n
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_I2C=n CONFIG_I2C=n
CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/esp32s2_franzininho/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_ESP32S2_FRANZININHO config BOARD_ESP32S2_FRANZININHO
bool "ESP32S2 Franzininho Board" bool "ESP32S2 Franzininho Board"
depends on SOC_ESP32S2 depends on SOC_SERIES_ESP32S2
choice SOC_PART_NUMBER
default SOC_ESP32S2_WROOM
endchoice

11
boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig
View file

@ -1,20 +1,13 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ESP32S2_FRANZININHO=y CONFIG_BOARD_ESP32S2_FRANZININHO=y
CONFIG_SOC_ESP32S2=y CONFIG_SOC_SERIES_ESP32S2=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y

10
boards/xtensa/esp32s2_saola/Kconfig.board
View file

@ -1,8 +1,10 @@
# ESP32S2 saola board configuration # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
config BOARD_ESP32S2_SAOLA config BOARD_ESP32S2_SAOLA
bool "ESP32S2 Saola Board" bool "ESP32S2 Saola Board"
depends on SOC_ESP32S2 depends on SOC_SERIES_ESP32S2
choice SOC_PART_NUMBER
default SOC_ESP32S2_WROVER_N4R2
endchoice

12
boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig
View file

@ -1,20 +1,12 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ESP32S2_SAOLA=y CONFIG_BOARD_ESP32S2_SAOLA=y
CONFIG_SOC_ESP32S2=y CONFIG_SOC_SERIES_ESP32S2=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y

9
boards/xtensa/esp32s3_devkitm/Kconfig.board
View file

@ -1,8 +1,11 @@
# ESP32S3 DevKitM board configuration
# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. # Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# ESP32S3 DevKitM board configuration
config BOARD_ESP32S3_DEVKITM config BOARD_ESP32S3_DEVKITM
bool "ESP32S3 DevKitM Board" bool "ESP32S3 DevKitM Board"
depends on SOC_ESP32S3 depends on SOC_SERIES_ESP32S3
choice SOC_PART_NUMBER
default SOC_ESP32S3_MINI_N8
endchoice

8
boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig
View file

@ -1,14 +1,12 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ESP32S3_DEVKITM=y CONFIG_BOARD_ESP32S3_DEVKITM=y
CONFIG_SOC_ESP32S3=y CONFIG_SOC_SERIES_ESP32S3=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/esp_wrover_kit/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_ESP_WROVER_KIT config BOARD_ESP_WROVER_KIT
bool "ESP-WROVER-KIT Development Board" bool "ESP-WROVER-KIT Development Board"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
choice SOC_PART_NUMBER
default SOC_ESP32_WROVER_E_N4R8
endchoice

11
boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig
View file

@ -1,9 +1,7 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ESP_WROVER_KIT=y CONFIG_BOARD_ESP_WROVER_KIT=y
CONFIG_SOC_ESP32=y CONFIG_SOC_SERIES_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
@ -11,11 +9,4 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_HELTEC_WIFI_LORA32 config BOARD_HELTEC_WIFI_LORA32
bool "HELTEC WiFi LoRa 32 (V2) Board" bool "HELTEC WiFi LoRa 32 (V2) Board"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
choice SOC_PART_NUMBER
default SOC_ESP32_D0WD_V3
endchoice

11
boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig
View file

@ -1,9 +1,7 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_HELTEC_WIFI_LORA32=y CONFIG_BOARD_HELTEC_WIFI_LORA32=y
CONFIG_SOC_ESP32=y CONFIG_SOC_SERIES_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
@ -11,11 +9,4 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/m5stickc_plus/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_M5STICKC_PLUS config BOARD_M5STICKC_PLUS
bool "M5StickC PLUS Development Board" bool "M5StickC PLUS Development Board"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
choice SOC_PART_NUMBER
default SOC_ESP32_PICO_D4
endchoice

11
boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig
View file

@ -1,9 +1,7 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_M5STICKC_PLUS=y CONFIG_BOARD_M5STICKC_PLUS=y
CONFIG_SOC_ESP32=y CONFIG_SOC_SERIES_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
@ -11,12 +9,5 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_I2C=y CONFIG_I2C=y
CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/odroid_go/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_ODROID_GO config BOARD_ODROID_GO
bool "ODROID-GO Game Kit" bool "ODROID-GO Game Kit"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
choice SOC_PART_NUMBER
default SOC_ESP32_WROVER_E_N16R2
endchoice

11
boards/xtensa/odroid_go/odroid_go_defconfig
View file

@ -1,9 +1,7 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ODROID_GO=y CONFIG_BOARD_ODROID_GO=y
CONFIG_SOC_ESP32=y CONFIG_SOC_SERIES_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
@ -11,14 +9,7 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y
# required to enable LCD backlight # required to enable LCD backlight
CONFIG_REGULATOR=y CONFIG_REGULATOR=y

6
boards/xtensa/olimex_esp32_evb/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_OLIMEX_ESP32_EVB config BOARD_OLIMEX_ESP32_EVB
bool "Olimex ESP32-EVB" bool "Olimex ESP32-EVB"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
choice SOC_PART_NUMBER
default SOC_ESP32_WROVER_E_N8R2
endchoice

11
boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig
View file

@ -1,9 +1,7 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_OLIMEX_ESP32_EVB=y CONFIG_BOARD_OLIMEX_ESP32_EVB=y
CONFIG_SOC_ESP32=y CONFIG_SOC_SERIES_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
@ -11,11 +9,4 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y

6
boards/xtensa/xiao_esp32s3/Kconfig.board
View file

@ -5,4 +5,8 @@
config BOARD_XIAO_ESP32S3 config BOARD_XIAO_ESP32S3
bool "XIAO ESP32S3 Board" bool "XIAO ESP32S3 Board"
depends on SOC_ESP32S3 depends on SOC_SERIES_ESP32S3
choice SOC_PART_NUMBER
default SOC_ESP32S3_WROOM_N8R8
endchoice

7
boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig
View file

@ -1,14 +1,9 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_XIAO_ESP32S3=y CONFIG_BOARD_XIAO_ESP32S3=y
CONFIG_SOC_ESP32S3=y CONFIG_SOC_SERIES_ESP32S3=y
CONFIG_MAIN_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_XTENSA_USE_CORE_CRT1=n
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_CLOCK_CONTROL=y

14
drivers/adc/adc_esp32.c
View file

@ -20,7 +20,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL); LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL);
#if CONFIG_SOC_ESP32 #if CONFIG_SOC_SERIES_ESP32
#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_VREF #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_VREF
#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MIN_BITWIDTH #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MIN_BITWIDTH
#define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH
@ -31,12 +31,12 @@ LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL);
*/ */
#define ADC_CLIP_MVOLT_11DB 2550 #define ADC_CLIP_MVOLT_11DB 2550
#elif CONFIG_SOC_ESP32S2 #elif CONFIG_SOC_SERIES_ESP32S2
#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP
#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH
#define ADC_RESOLUTION_MAX SOC_ADC_MAX_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_MAX_BITWIDTH
#elif CONFIG_SOC_ESP32C3 #elif CONFIG_SOC_SERIES_ESP32C3
#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP
#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH
#define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH
@ -165,14 +165,14 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
data->resolution[channel_id] = seq->resolution; data->resolution[channel_id] = seq->resolution;
#if CONFIG_SOC_ESP32C3 #if CONFIG_SOC_SERIES_ESP32C3
/* NOTE: nothing to set on ESP32C3 SoC */ /* NOTE: nothing to set on ESP32C3 SoC */
if (conf->unit == ADC_UNIT_1) { if (conf->unit == ADC_UNIT_1) {
adc1_config_width(ADC_WIDTH_BIT_DEFAULT); adc1_config_width(ADC_WIDTH_BIT_DEFAULT);
} }
#else #else
adc_set_data_width(conf->unit, WIDTH_MASK(data->resolution[channel_id])); adc_set_data_width(conf->unit, WIDTH_MASK(data->resolution[channel_id]));
#endif /* CONFIG_SOC_ESP32C3 */ #endif /* CONFIG_SOC_SERIES_ESP32C3 */
/* Read raw value */ /* Read raw value */
if (conf->unit == ADC_UNIT_1) { if (conf->unit == ADC_UNIT_1) {
@ -191,13 +191,13 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
/* Get corrected voltage output */ /* Get corrected voltage output */
cal = cal_mv = esp_adc_cal_raw_to_voltage(reading, &data->chars[channel_id]); cal = cal_mv = esp_adc_cal_raw_to_voltage(reading, &data->chars[channel_id]);
#if CONFIG_SOC_ESP32 #if CONFIG_SOC_SERIES_ESP32
if (data->attenuation[channel_id] == ADC_ATTEN_DB_11) { if (data->attenuation[channel_id] == ADC_ATTEN_DB_11) {
if (cal > ADC_CLIP_MVOLT_11DB) { if (cal > ADC_CLIP_MVOLT_11DB) {
cal = ADC_CLIP_MVOLT_11DB; cal = ADC_CLIP_MVOLT_11DB;
} }
} }
#endif /* CONFIG_SOC_ESP32 */ #endif /* CONFIG_SOC_SERIES_ESP32 */
/* Fit according to selected attenuation */ /* Fit according to selected attenuation */
atten_to_gain(data->attenuation[channel_id], &cal); atten_to_gain(data->attenuation[channel_id], &cal);

2
drivers/bluetooth/hci/hci_esp32.c
View file

@ -280,7 +280,7 @@ static int bt_esp32_ble_init(void)
int ret; int ret;
esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
#if defined(CONFIG_BT_BREDR) && defined(CONFIG_SOC_ESP32) #if defined(CONFIG_BT_BREDR) && defined(CONFIG_SOC_SERIES_ESP32)
esp_bt_mode_t mode = ESP_BT_MODE_BTDM; esp_bt_mode_t mode = ESP_BT_MODE_BTDM;
#else #else
esp_bt_mode_t mode = ESP_BT_MODE_BLE; esp_bt_mode_t mode = ESP_BT_MODE_BLE;

30
drivers/can/can_esp32_twai.c
View file

@ -26,7 +26,7 @@ LOG_MODULE_REGISTER(can_esp32_twai, CONFIG_CAN_LOG_LEVEL);
* The names with TWAI_ prefixes from Espressif reference manuals are used for these incompatible * The names with TWAI_ prefixes from Espressif reference manuals are used for these incompatible
* registers. * registers.
*/ */
#ifndef CONFIG_SOC_ESP32 #ifndef CONFIG_SOC_SERIES_ESP32
/* TWAI_BUS_TIMING_0_REG is incompatible with CAN_SJA1000_BTR0 */ /* TWAI_BUS_TIMING_0_REG is incompatible with CAN_SJA1000_BTR0 */
#define TWAI_BUS_TIMING_0_REG (6U) #define TWAI_BUS_TIMING_0_REG (6U)
@ -63,7 +63,7 @@ LOG_MODULE_REGISTER(can_esp32_twai, CONFIG_CAN_LOG_LEVEL);
#define TWAI_CD_MASK GENMASK(2, 0) #define TWAI_CD_MASK GENMASK(2, 0)
#define TWAI_CLOCK_OFF BIT(3) #define TWAI_CLOCK_OFF BIT(3)
#endif /* !CONFIG_SOC_ESP32 */ #endif /* !CONFIG_SOC_SERIES_ESP32 */
struct can_esp32_twai_config { struct can_esp32_twai_config {
mm_reg_t base; mm_reg_t base;
@ -71,10 +71,10 @@ struct can_esp32_twai_config {
const struct device *clock_dev; const struct device *clock_dev;
const clock_control_subsys_t clock_subsys; const clock_control_subsys_t clock_subsys;
int irq_source; int irq_source;
#ifndef CONFIG_SOC_ESP32 #ifndef CONFIG_SOC_SERIES_ESP32
/* 32-bit variant of output clock divider register required for non-ESP32 MCUs */ /* 32-bit variant of output clock divider register required for non-ESP32 MCUs */
uint32_t cdr32; uint32_t cdr32;
#endif /* !CONFIG_SOC_ESP32 */ #endif /* !CONFIG_SOC_SERIES_ESP32 */
}; };
static uint8_t can_esp32_twai_read_reg(const struct device *dev, uint8_t reg) static uint8_t can_esp32_twai_read_reg(const struct device *dev, uint8_t reg)
@ -95,7 +95,7 @@ static void can_esp32_twai_write_reg(const struct device *dev, uint8_t reg, uint
sys_write32(val & 0xFF, addr); sys_write32(val & 0xFF, addr);
} }
#ifndef CONFIG_SOC_ESP32 #ifndef CONFIG_SOC_SERIES_ESP32
/* /*
* Required for newer ESP32-series MCUs which violate the original SJA1000 8-bit register size. * Required for newer ESP32-series MCUs which violate the original SJA1000 8-bit register size.
@ -157,7 +157,7 @@ static int can_esp32_twai_set_timing(const struct device *dev, const struct can_
return 0; return 0;
} }
#endif /* !CONFIG_SOC_ESP32 */ #endif /* !CONFIG_SOC_SERIES_ESP32 */
static int can_esp32_twai_get_core_clock(const struct device *dev, uint32_t *rate) static int can_esp32_twai_get_core_clock(const struct device *dev, uint32_t *rate)
{ {
@ -205,7 +205,7 @@ static int can_esp32_twai_init(const struct device *dev)
return err; return err;
} }
#ifndef CONFIG_SOC_ESP32 #ifndef CONFIG_SOC_SERIES_ESP32
/* /*
* TWAI_CLOCK_DIVIDER_REG is incompatible with CAN_SJA1000_CDR for non-ESP32 MCUs * TWAI_CLOCK_DIVIDER_REG is incompatible with CAN_SJA1000_CDR for non-ESP32 MCUs
* - TWAI_CD has length of 8 bits instead of 3 bits * - TWAI_CD has length of 8 bits instead of 3 bits
@ -215,7 +215,7 @@ static int can_esp32_twai_init(const struct device *dev)
* Overwrite with 32-bit register variant configured via devicetree. * Overwrite with 32-bit register variant configured via devicetree.
*/ */
can_esp32_twai_write_reg32(dev, TWAI_CLOCK_DIVIDER_REG, twai_config->cdr32); can_esp32_twai_write_reg32(dev, TWAI_CLOCK_DIVIDER_REG, twai_config->cdr32);
#endif /* !CONFIG_SOC_ESP32 */ #endif /* !CONFIG_SOC_SERIES_ESP32 */
esp_intr_alloc(twai_config->irq_source, 0, can_esp32_twai_isr, (void *)dev, NULL); esp_intr_alloc(twai_config->irq_source, 0, can_esp32_twai_isr, (void *)dev, NULL);
@ -227,11 +227,11 @@ const struct can_driver_api can_esp32_twai_driver_api = {
.start = can_sja1000_start, .start = can_sja1000_start,
.stop = can_sja1000_stop, .stop = can_sja1000_stop,
.set_mode = can_sja1000_set_mode, .set_mode = can_sja1000_set_mode,
#ifdef CONFIG_SOC_ESP32 #ifdef CONFIG_SOC_SERIES_ESP32
.set_timing = can_sja1000_set_timing, .set_timing = can_sja1000_set_timing,
#else #else
.set_timing = can_esp32_twai_set_timing, .set_timing = can_esp32_twai_set_timing,
#endif /* CONFIG_SOC_ESP32 */ #endif /* CONFIG_SOC_SERIES_ESP32 */
.send = can_sja1000_send, .send = can_sja1000_send,
.add_rx_filter = can_sja1000_add_rx_filter, .add_rx_filter = can_sja1000_add_rx_filter,
.remove_rx_filter = can_sja1000_remove_rx_filter, .remove_rx_filter = can_sja1000_remove_rx_filter,
@ -244,7 +244,7 @@ const struct can_driver_api can_esp32_twai_driver_api = {
.recover = can_sja1000_recover, .recover = can_sja1000_recover,
#endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ #endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
.timing_min = CAN_SJA1000_TIMING_MIN_INITIALIZER, .timing_min = CAN_SJA1000_TIMING_MIN_INITIALIZER,
#ifdef CONFIG_SOC_ESP32 #ifdef CONFIG_SOC_SERIES_ESP32
.timing_max = CAN_SJA1000_TIMING_MAX_INITIALIZER, .timing_max = CAN_SJA1000_TIMING_MAX_INITIALIZER,
#else #else
/* larger prescaler allowed for newer ESP32-series MCUs */ /* larger prescaler allowed for newer ESP32-series MCUs */
@ -255,16 +255,16 @@ const struct can_driver_api can_esp32_twai_driver_api = {
.phase_seg2 = 0x8, .phase_seg2 = 0x8,
.prescaler = 0x2000, .prescaler = 0x2000,
} }
#endif /* CONFIG_SOC_ESP32 */ #endif /* CONFIG_SOC_SERIES_ESP32 */
}; };
#ifdef CONFIG_SOC_ESP32 #ifdef CONFIG_SOC_SERIES_ESP32
#define TWAI_CLKOUT_DIVIDER_MAX (14) #define TWAI_CLKOUT_DIVIDER_MAX (14)
#define TWAI_CDR32_INIT(inst) #define TWAI_CDR32_INIT(inst)
#else #else
#define TWAI_CLKOUT_DIVIDER_MAX (490) #define TWAI_CLKOUT_DIVIDER_MAX (490)
#define TWAI_CDR32_INIT(inst) .cdr32 = CAN_ESP32_TWAI_DT_CDR_INST_GET(inst) #define TWAI_CDR32_INIT(inst) .cdr32 = CAN_ESP32_TWAI_DT_CDR_INST_GET(inst)
#endif /* CONFIG_SOC_ESP32 */ #endif /* CONFIG_SOC_SERIES_ESP32 */
#define CAN_ESP32_TWAI_ASSERT_CLKOUT_DIVIDER(inst) \ #define CAN_ESP32_TWAI_ASSERT_CLKOUT_DIVIDER(inst) \
BUILD_ASSERT(COND_CODE_0(DT_INST_NODE_HAS_PROP(inst, clkout_divider), (1), \ BUILD_ASSERT(COND_CODE_0(DT_INST_NODE_HAS_PROP(inst, clkout_divider), (1), \
@ -295,7 +295,7 @@ const struct can_driver_api can_esp32_twai_driver_api = {
CAN_SJA1000_DT_CONFIG_INST_GET(inst, &can_esp32_twai_config_##inst, \ CAN_SJA1000_DT_CONFIG_INST_GET(inst, &can_esp32_twai_config_##inst, \
can_esp32_twai_read_reg, can_esp32_twai_write_reg, \ can_esp32_twai_read_reg, can_esp32_twai_write_reg, \
CAN_SJA1000_OCR_OCMODE_BIPHASE, \ CAN_SJA1000_OCR_OCMODE_BIPHASE, \
COND_CODE_0(IS_ENABLED(CONFIG_SOC_ESP32), (0), \ COND_CODE_0(IS_ENABLED(CONFIG_SOC_SERIES_ESP32), (0), \
(CAN_ESP32_TWAI_DT_CDR_INST_GET(inst)))); \ (CAN_ESP32_TWAI_DT_CDR_INST_GET(inst)))); \
\ \
static struct can_sja1000_data can_sja1000_data_##inst = \ static struct can_sja1000_data can_sja1000_data_##inst = \

36
drivers/clock_control/clock_control_esp32.c
View file

@ -9,32 +9,32 @@
#define CPU_RESET_REASON RTC_SW_CPU_RESET #define CPU_RESET_REASON RTC_SW_CPU_RESET
#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) #if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32_NET)
#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6 #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6
#undef CPU_RESET_REASON #undef CPU_RESET_REASON
#define CPU_RESET_REASON SW_CPU_RESET #define CPU_RESET_REASON SW_CPU_RESET
#include <zephyr/dt-bindings/clock/esp32_clock.h> #include <zephyr/dt-bindings/clock/esp32_clock.h>
#include "esp32/rom/rtc.h" #include "esp32/rom/rtc.h"
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#elif defined(CONFIG_SOC_ESP32S2) #elif defined(CONFIG_SOC_SERIES_ESP32S2)
#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
#include <zephyr/dt-bindings/clock/esp32s2_clock.h> #include <zephyr/dt-bindings/clock/esp32s2_clock.h>
#include "esp32s2/rom/rtc.h" #include "esp32s2/rom/rtc.h"
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#elif defined(CONFIG_SOC_ESP32S3) #elif defined(CONFIG_SOC_SERIES_ESP32S3)
#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
#include <zephyr/dt-bindings/clock/esp32s3_clock.h> #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
#include "esp32s3/rom/rtc.h" #include "esp32s3/rom/rtc.h"
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#include "esp32s3/clk.h" #include "esp32s3/clk.h"
#elif CONFIG_IDF_TARGET_ESP32C3 #elif CONFIG_SOC_SERIES_ESP32C3
#define DT_CPU_COMPAT espressif_riscv #define DT_CPU_COMPAT espressif_riscv
#include <zephyr/dt-bindings/clock/esp32c3_clock.h> #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
#include "esp32c3/rom/rtc.h" #include "esp32c3/rom/rtc.h"
#include <soc/soc_caps.h> #include <soc/soc_caps.h>
#include <soc/soc.h> #include <soc/soc.h>
#include <soc/rtc.h> #include <soc/rtc.h>
#endif #endif /* CONFIG_SOC_SERIES_ESP32xx */
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#include <soc/rtc.h> #include <soc/rtc.h>
@ -55,14 +55,16 @@ struct esp32_clock_config {
}; };
static uint8_t const xtal_freq[] = { static uint8_t const xtal_freq[] = {
#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) || defined(CONFIG_SOC_ESP32S3) #if defined(CONFIG_SOC_SERIES_ESP32) || \
defined(CONFIG_SOC_SERIES_ESP32_NET) || \
defined(CONFIG_SOC_SERIES_ESP32S3)
[ESP32_CLK_XTAL_24M] = 24, [ESP32_CLK_XTAL_24M] = 24,
[ESP32_CLK_XTAL_26M] = 26, [ESP32_CLK_XTAL_26M] = 26,
[ESP32_CLK_XTAL_40M] = 40, [ESP32_CLK_XTAL_40M] = 40,
[ESP32_CLK_XTAL_AUTO] = 0 [ESP32_CLK_XTAL_AUTO] = 0
#elif defined(CONFIG_SOC_ESP32S2) #elif defined(CONFIG_SOC_SERIES_ESP32S2)
[ESP32_CLK_XTAL_40M] = 40, [ESP32_CLK_XTAL_40M] = 40,
#elif defined(CONFIG_SOC_ESP32C3) #elif defined(CONFIG_SOC_SERIES_ESP32C3)
[ESP32_CLK_XTAL_32M] = 32, [ESP32_CLK_XTAL_32M] = 32,
[ESP32_CLK_XTAL_40M] = 40, [ESP32_CLK_XTAL_40M] = 40,
#endif #endif
@ -124,7 +126,7 @@ static int clock_control_esp32_get_rate(const struct device *dev,
return 0; return 0;
} }
#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) #if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32_NET)
static void esp32_clock_perip_init(void) static void esp32_clock_perip_init(void)
{ {
uint32_t common_perip_clk; uint32_t common_perip_clk;
@ -217,9 +219,9 @@ static void esp32_clock_perip_init(void)
/* Enable RNG clock. */ /* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE); periph_module_enable(PERIPH_RNG_MODULE);
} }
#endif #endif /* CONFIG_SOC_SERIES_ESP32 */
#if defined(CONFIG_SOC_ESP32S2) #if defined(CONFIG_SOC_SERIES_ESP32S2)
static void esp32_clock_perip_init(void) static void esp32_clock_perip_init(void)
{ {
uint32_t common_perip_clk; uint32_t common_perip_clk;
@ -321,9 +323,9 @@ static void esp32_clock_perip_init(void)
/* Enable RNG clock. */ /* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE); periph_module_enable(PERIPH_RNG_MODULE);
} }
#endif #endif /* CONFIG_SOC_SERIES_ESP32S2 */
#if defined(CONFIG_SOC_ESP32S3) #if defined(CONFIG_SOC_SERIES_ESP32S3)
static void esp32_clock_perip_init(void) static void esp32_clock_perip_init(void)
{ {
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
@ -421,9 +423,9 @@ static void esp32_clock_perip_init(void)
esp_rom_uart_tx_wait_idle(0); esp_rom_uart_tx_wait_idle(0);
esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200); esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200);
} }
#endif #endif /* CONFIG_SOC_SERIES_ESP32S3 */
#if defined(CONFIG_SOC_ESP32C3) #if defined(CONFIG_SOC_SERIES_ESP32C3)
static void esp32_clock_perip_init(void) static void esp32_clock_perip_init(void)
{ {
uint32_t common_perip_clk; uint32_t common_perip_clk;
@ -510,7 +512,7 @@ static void esp32_clock_perip_init(void)
/* Enable RNG clock. */ /* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE); periph_module_enable(PERIPH_RNG_MODULE);
} }
#endif #endif /* CONFIG_SOC_SERIES_ESP32C3 */
static int clock_control_esp32_init(const struct device *dev) static int clock_control_esp32_init(const struct device *dev)
{ {
@ -596,7 +598,7 @@ DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
&clock_control_esp32_api); &clock_control_esp32_api);
#ifndef CONFIG_SOC_ESP32C3 #ifndef CONFIG_SOC_SERIES_ESP32C3
BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) == BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency), DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency),
"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq"); "SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");

6
drivers/counter/counter_esp32_rtc.c
View file

@ -18,7 +18,7 @@
#include <zephyr/spinlock.h> #include <zephyr/spinlock.h>
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#if defined(CONFIG_SOC_ESP32C3) #if defined(CONFIG_SOC_SERIES_ESP32C3)
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h> #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#else #else
#include <zephyr/drivers/interrupt_controller/intc_esp32.h> #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
@ -27,7 +27,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(esp32_counter_rtc, CONFIG_COUNTER_LOG_LEVEL); LOG_MODULE_REGISTER(esp32_counter_rtc, CONFIG_COUNTER_LOG_LEVEL);
#if defined(CONFIG_SOC_ESP32C3) #if defined(CONFIG_SOC_SERIES_ESP32C3)
#define ESP32_COUNTER_RTC_ISR_HANDLER isr_handler_t #define ESP32_COUNTER_RTC_ISR_HANDLER isr_handler_t
#else #else
#define ESP32_COUNTER_RTC_ISR_HANDLER intr_handler_t #define ESP32_COUNTER_RTC_ISR_HANDLER intr_handler_t
@ -88,7 +88,7 @@ static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks)
ARG_UNUSED(dev); ARG_UNUSED(dev);
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
#if defined(CONFIG_SOC_ESP32) #if defined(CONFIG_SOC_SERIES_ESP32)
while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) { while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
/* might take 1 RTC slowclk period, don't flood RTC bus */ /* might take 1 RTC slowclk period, don't flood RTC bus */
k_sleep(K_USEC(1)); k_sleep(K_USEC(1));

4
drivers/counter/counter_esp32_tmr.c
View file

@ -17,7 +17,7 @@
#include <zephyr/drivers/counter.h> #include <zephyr/drivers/counter.h>
#include <zephyr/spinlock.h> #include <zephyr/spinlock.h>
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#ifndef CONFIG_SOC_ESP32C3 #ifndef CONFIG_SOC_SERIES_ESP32C3
#include <zephyr/drivers/interrupt_controller/intc_esp32.h> #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#else #else
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h> #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
@ -26,7 +26,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(esp32_counter, CONFIG_COUNTER_LOG_LEVEL); LOG_MODULE_REGISTER(esp32_counter, CONFIG_COUNTER_LOG_LEVEL);
#ifdef CONFIG_SOC_ESP32C3 #ifdef CONFIG_SOC_SERIES_ESP32C3
#define ISR_HANDLER isr_handler_t #define ISR_HANDLER isr_handler_t
#else #else
#define ISR_HANDLER intr_handler_t #define ISR_HANDLER intr_handler_t

10
drivers/dma/dma_esp32_gdma.c
View file

@ -21,13 +21,13 @@ LOG_MODULE_REGISTER(dma_esp32_gdma, CONFIG_DMA_LOG_LEVEL);
#include <zephyr/drivers/dma.h> #include <zephyr/drivers/dma.h>
#include <zephyr/drivers/dma/dma_esp32.h> #include <zephyr/drivers/dma/dma_esp32.h>
#include <zephyr/drivers/clock_control.h> #include <zephyr/drivers/clock_control.h>
#ifndef CONFIG_SOC_ESP32C3 #ifndef CONFIG_SOC_SERIES_ESP32C3
#include <zephyr/drivers/interrupt_controller/intc_esp32.h> #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#else #else
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h> #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#endif #endif
#ifdef CONFIG_SOC_ESP32C3 #ifdef CONFIG_SOC_SERIES_ESP32C3
#define ISR_HANDLER isr_handler_t #define ISR_HANDLER isr_handler_t
#else #else
#define ISR_HANDLER intr_handler_t #define ISR_HANDLER intr_handler_t
@ -53,7 +53,7 @@ struct dma_esp32_channel {
dma_callback_t cb; dma_callback_t cb;
void *user_data; void *user_data;
dma_descriptor_t desc; dma_descriptor_t desc;
#if defined(CONFIG_SOC_ESP32S3) #if defined(CONFIG_SOC_SERIES_ESP32S3)
struct intr_handle_data_t *intr_handle; struct intr_handle_data_t *intr_handle;
#endif #endif
}; };
@ -120,7 +120,7 @@ static void IRAM_ATTR dma_esp32_isr_handle(const struct device *dev, uint8_t rx_
} }
} }
#if defined(CONFIG_SOC_ESP32C3) #if defined(CONFIG_SOC_SERIES_ESP32C3)
static int dma_esp32_enable_interrupt(const struct device *dev, static int dma_esp32_enable_interrupt(const struct device *dev,
struct dma_esp32_channel *dma_channel) struct dma_esp32_channel *dma_channel)
{ {
@ -467,7 +467,7 @@ static int dma_esp32_reload(const struct device *dev, uint32_t channel, uint32_t
return 0; return 0;
} }
#if defined(CONFIG_SOC_ESP32C3) #if defined(CONFIG_SOC_SERIES_ESP32C3)
static int dma_esp32_configure_irq(const struct device *dev) static int dma_esp32_configure_irq(const struct device *dev)
{ {
struct dma_esp32_config *config = (struct dma_esp32_config *)dev->config; struct dma_esp32_config *config = (struct dma_esp32_config *)dev->config;

2
drivers/ethernet/Kconfig.esp32
View file

@ -5,7 +5,7 @@
menuconfig ETH_ESP32 menuconfig ETH_ESP32
bool "ESP32 Ethernet driver" bool "ESP32 Ethernet driver"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
select MDIO select MDIO
help help
Enable ESP32 Ethernet driver. Enable ESP32 Ethernet driver.

8
drivers/flash/flash_esp32.c
View file

@ -30,20 +30,20 @@
#include <zephyr/drivers/flash.h> #include <zephyr/drivers/flash.h>
#include <soc.h> #include <soc.h>
#if defined(CONFIG_SOC_ESP32) #if defined(CONFIG_SOC_SERIES_ESP32)
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#include "esp32/rom/cache.h" #include "esp32/rom/cache.h"
#include "esp32/rom/spi_flash.h" #include "esp32/rom/spi_flash.h"
#include "esp32/spiram.h" #include "esp32/spiram.h"
#elif defined(CONFIG_SOC_ESP32S2) #elif defined(CONFIG_SOC_SERIES_ESP32S2)
#include "soc/spi_mem_reg.h" #include "soc/spi_mem_reg.h"
#include "esp32s2/rom/cache.h" #include "esp32s2/rom/cache.h"
#include "esp32s2/rom/spi_flash.h" #include "esp32s2/rom/spi_flash.h"
#elif defined(CONFIG_SOC_ESP32S3) #elif defined(CONFIG_SOC_SERIES_ESP32S3)
#include "soc/spi_mem_reg.h" #include "soc/spi_mem_reg.h"
#include "esp32s3/rom/cache.h" #include "esp32s3/rom/cache.h"
#include "esp32s3/rom/spi_flash.h" #include "esp32s3/rom/spi_flash.h"
#elif defined(CONFIG_SOC_ESP32C3) #elif defined(CONFIG_SOC_SERIES_ESP32C3)
#include "soc/spi_periph.h" #include "soc/spi_periph.h"
#include "soc/spi_mem_reg.h" #include "soc/spi_mem_reg.h"
#include "soc/dport_access.h" #include "soc/dport_access.h"

4
drivers/gpio/gpio_esp32.c
View file

@ -20,7 +20,7 @@
#include <zephyr/device.h> #include <zephyr/device.h>
#include <zephyr/drivers/gpio.h> #include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/espressif-esp32-gpio.h> #include <zephyr/dt-bindings/gpio/espressif-esp32-gpio.h>
#ifdef CONFIG_SOC_ESP32C3 #ifdef CONFIG_SOC_SERIES_ESP32C3
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h> #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#else #else
#include <zephyr/drivers/interrupt_controller/intc_esp32.h> #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
@ -33,7 +33,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL); LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
#ifdef CONFIG_SOC_ESP32C3 #ifdef CONFIG_SOC_SERIES_ESP32C3
/* gpio structs in esp32c3 series are different from xtensa ones */ /* gpio structs in esp32c3 series are different from xtensa ones */
#define out out.data #define out out.data
#define in in.data #define in in.data

2
drivers/hwinfo/hwinfo_esp32.c
View file

@ -15,7 +15,7 @@
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{ {
#if !defined(CONFIG_SOC_ESP32) && !defined(CONFIG_SOC_ESP32_NET) #if !defined(CONFIG_SOC_SERIES_ESP32) && !defined(CONFIG_SOC_SERIES_ESP32_NET)
uint32_t rdata1 = sys_read32(EFUSE_RD_MAC_SPI_SYS_0_REG); uint32_t rdata1 = sys_read32(EFUSE_RD_MAC_SPI_SYS_0_REG);
uint32_t rdata2 = sys_read32(EFUSE_RD_MAC_SPI_SYS_1_REG); uint32_t rdata2 = sys_read32(EFUSE_RD_MAC_SPI_SYS_1_REG);
#else #else

2
drivers/i2c/i2c_esp32.c
View file

@ -255,7 +255,7 @@ static void IRAM_ATTR i2c_esp32_configure_timeout(const struct device *dev)
* at least for ESP32-C3 (tested with communication to bq76952 chip). So we set the * at least for ESP32-C3 (tested with communication to bq76952 chip). So we set the
* timeout to maximum supported value instead. * timeout to maximum supported value instead.
*/ */
#if defined(CONFIG_SOC_ESP32C3) || defined(CONFIG_SOC_ESP32) #if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32)
i2c_hal_set_tout(&data->hal, I2C_LL_MAX_TIMEOUT); i2c_hal_set_tout(&data->hal, I2C_LL_MAX_TIMEOUT);
#else #else
i2c_hal_set_tout_en(&data->hal, 0); i2c_hal_set_tout_en(&data->hal, 0);

2
drivers/interrupt_controller/Kconfig.esp32
View file

@ -5,7 +5,7 @@
config INTC_ESP32 config INTC_ESP32
bool "Interrupt allocator for Xtensa-based Espressif SoCs" bool "Interrupt allocator for Xtensa-based Espressif SoCs"
default y if SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32_NET || SOC_ESP32S3 default y if SOC_FAMILY_ESP32 && !SOC_SERIES_ESP32C3
help help
Enable custom interrupt allocator for Espressif SoCs based on Xtensa Enable custom interrupt allocator for Espressif SoCs based on Xtensa
architecture. architecture.

2
drivers/interrupt_controller/Kconfig.esp32c3
View file

@ -3,7 +3,7 @@
config INTC_ESP32C3 config INTC_ESP32C3
bool "ESP32C3 interrupt controller driver" bool "ESP32C3 interrupt controller driver"
depends on SOC_ESP32C3 depends on SOC_SERIES_ESP32C3
default y default y
help help
Enables the esp32c3 interrupt controller driver to handle ISR Enables the esp32c3 interrupt controller driver to handle ISR

2
drivers/mdio/Kconfig.esp32
View file

@ -3,7 +3,7 @@
config MDIO_ESP32 config MDIO_ESP32
bool "ESP32 MDIO driver" bool "ESP32 MDIO driver"
depends on SOC_ESP32 depends on SOC_SERIES_ESP32
default y default y
help help
Enable ESP32 MCU Family MDIO driver. Enable ESP32 MCU Family MDIO driver.

2
drivers/pinctrl/pinctrl_esp32.c
View file

@ -12,7 +12,7 @@
#include <zephyr/drivers/pinctrl.h> #include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pinctrl/pinctrl_esp32_common.h> #include <zephyr/drivers/pinctrl/pinctrl_esp32_common.h>
#ifdef CONFIG_SOC_ESP32C3 #ifdef CONFIG_SOC_SERIES_ESP32C3
/* gpio structs in esp32c3 series are different from xtensa ones */ /* gpio structs in esp32c3 series are different from xtensa ones */
#define out out.data #define out out.data
#define in in.data #define in in.data

2
drivers/sensor/esp32_temp/Kconfig
View file

@ -5,6 +5,6 @@ config ESP32_TEMP
bool "ESP32 Temperature Sensor" bool "ESP32 Temperature Sensor"
default y default y
depends on DT_HAS_ESPRESSIF_ESP32_TEMP_ENABLED depends on DT_HAS_ESPRESSIF_ESP32_TEMP_ENABLED
depends on !SOC_ESP32 depends on !SOC_SERIES_ESP32
help help
Enable driver for temperature sensor on certain ESP targets. Enable driver for temperature sensor on certain ESP targets.

2
drivers/sensor/esp32_temp/esp32_temp.c
View file

@ -16,7 +16,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(esp32_temp, CONFIG_SENSOR_LOG_LEVEL); LOG_MODULE_REGISTER(esp32_temp, CONFIG_SENSOR_LOG_LEVEL);
#if CONFIG_SOC_ESP32 #if CONFIG_SOC_SERIES_ESP32
#error "Temperature sensor not supported on ESP32" #error "Temperature sensor not supported on ESP32"
#endif /* CONFIG_IDF_TARGET_ESP32 */ #endif /* CONFIG_IDF_TARGET_ESP32 */

8
drivers/sensor/pcnt_esp32/pcnt_esp32.c
View file

@ -29,12 +29,12 @@ LOG_MODULE_REGISTER(pcnt_esp32, CONFIG_SENSOR_LOG_LEVEL);
#define PCNT_INTR_UNIT_1 BIT(1) #define PCNT_INTR_UNIT_1 BIT(1)
#define PCNT_INTR_UNIT_2 BIT(2) #define PCNT_INTR_UNIT_2 BIT(2)
#define PCNT_INTR_UNIT_3 BIT(3) #define PCNT_INTR_UNIT_3 BIT(3)
#ifdef CONFIG_SOC_ESP32 #ifdef CONFIG_SOC_SERIES_ESP32
#define PCNT_INTR_UNIT_4 BIT(4) #define PCNT_INTR_UNIT_4 BIT(4)
#define PCNT_INTR_UNIT_5 BIT(5) #define PCNT_INTR_UNIT_5 BIT(5)
#define PCNT_INTR_UNIT_6 BIT(6) #define PCNT_INTR_UNIT_6 BIT(6)
#define PCNT_INTR_UNIT_7 BIT(7) #define PCNT_INTR_UNIT_7 BIT(7)
#endif /* CONFIG_SOC_ESP32 */ #endif /* CONFIG_SOC_SERIES_ESP32 */
#ifdef CONFIG_PCNT_ESP32_TRIGGER #ifdef CONFIG_PCNT_ESP32_TRIGGER
#define PCNT_INTR_THRES_1 BIT(2) #define PCNT_INTR_THRES_1 BIT(2)
@ -293,7 +293,7 @@ static void IRAM_ATTR pcnt_esp32_isr(const struct device *dev)
pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 2); pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 2);
} else if (pcnt_intr_status & PCNT_INTR_UNIT_3) { } else if (pcnt_intr_status & PCNT_INTR_UNIT_3) {
pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 3); pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 3);
#ifdef CONFIG_SOC_ESP32 #ifdef CONFIG_SOC_SERIES_ESP32
} else if (pcnt_intr_status & PCNT_INTR_UNIT_4) { } else if (pcnt_intr_status & PCNT_INTR_UNIT_4) {
pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 4); pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 4);
} else if (pcnt_intr_status & PCNT_INTR_UNIT_5) { } else if (pcnt_intr_status & PCNT_INTR_UNIT_5) {
@ -302,7 +302,7 @@ static void IRAM_ATTR pcnt_esp32_isr(const struct device *dev)
pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 6); pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 6);
} else if (pcnt_intr_status & PCNT_INTR_UNIT_7) { } else if (pcnt_intr_status & PCNT_INTR_UNIT_7) {
pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 7); pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 7);
#endif /* CONFIG_SOC_ESP32 */ #endif /* CONFIG_SOC_SERIES_ESP32 */
} else { } else {
return; return;
} }

2
drivers/serial/Kconfig.esp32
View file

@ -7,7 +7,7 @@ config UART_ESP32
depends on DT_HAS_ESPRESSIF_ESP32_UART_ENABLED depends on DT_HAS_ESPRESSIF_ESP32_UART_ENABLED
select SERIAL_HAS_DRIVER select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT select SERIAL_SUPPORT_INTERRUPT
select SERIAL_SUPPORT_ASYNC if (SOC_ESP32C3 || SOC_ESP32S3) select SERIAL_SUPPORT_ASYNC if (SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32S3)
select GPIO_ESP32 select GPIO_ESP32
help help
Enable the ESP32 UART. Enable the ESP32 UART.

12
drivers/serial/uart_esp32.c
View file

@ -9,19 +9,19 @@
/* Include esp-idf headers first to avoid redefining BIT() macro */ /* Include esp-idf headers first to avoid redefining BIT() macro */
/* TODO: include w/o prefix */ /* TODO: include w/o prefix */
#ifdef CONFIG_SOC_ESP32 #ifdef CONFIG_SOC_SERIES_ESP32
#include <esp32/rom/ets_sys.h> #include <esp32/rom/ets_sys.h>
#include <esp32/rom/gpio.h> #include <esp32/rom/gpio.h>
#include <soc/dport_reg.h> #include <soc/dport_reg.h>
#elif defined(CONFIG_SOC_ESP32S2) #elif defined(CONFIG_SOC_SERIES_ESP32S2)
#include <esp32s2/rom/ets_sys.h> #include <esp32s2/rom/ets_sys.h>
#include <esp32s2/rom/gpio.h> #include <esp32s2/rom/gpio.h>
#include <soc/dport_reg.h> #include <soc/dport_reg.h>
#elif defined(CONFIG_SOC_ESP32S3) #elif defined(CONFIG_SOC_SERIES_ESP32S3)
#include <esp32s3/rom/ets_sys.h> #include <esp32s3/rom/ets_sys.h>
#include <esp32s3/rom/gpio.h> #include <esp32s3/rom/gpio.h>
#include <zephyr/dt-bindings/clock/esp32s3_clock.h> #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
#elif defined(CONFIG_SOC_ESP32C3) #elif defined(CONFIG_SOC_SERIES_ESP32C3)
#include <esp32c3/rom/ets_sys.h> #include <esp32c3/rom/ets_sys.h>
#include <esp32c3/rom/gpio.h> #include <esp32c3/rom/gpio.h>
#include <zephyr/dt-bindings/clock/esp32c3_clock.h> #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
@ -43,7 +43,7 @@
#include <soc.h> #include <soc.h>
#include <zephyr/drivers/uart.h> #include <zephyr/drivers/uart.h>
#ifndef CONFIG_SOC_ESP32C3 #ifndef CONFIG_SOC_SERIES_ESP32C3
#include <zephyr/drivers/interrupt_controller/intc_esp32.h> #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#else #else
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h> #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
@ -55,7 +55,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(uart_esp32, CONFIG_UART_LOG_LEVEL); LOG_MODULE_REGISTER(uart_esp32, CONFIG_UART_LOG_LEVEL);
#ifdef CONFIG_SOC_ESP32C3 #ifdef CONFIG_SOC_SERIES_ESP32C3
#define ISR_HANDLER isr_handler_t #define ISR_HANDLER isr_handler_t
#else #else
#define ISR_HANDLER intr_handler_t #define ISR_HANDLER intr_handler_t

12
drivers/spi/spi_esp32_spim.c
View file

@ -16,7 +16,7 @@ LOG_MODULE_REGISTER(esp32_spi, CONFIG_SPI_LOG_LEVEL);
#include <soc.h> #include <soc.h>
#include <soc/soc_memory_types.h> #include <soc/soc_memory_types.h>
#include <zephyr/drivers/spi.h> #include <zephyr/drivers/spi.h>
#ifndef CONFIG_SOC_ESP32C3 #ifndef CONFIG_SOC_SERIES_ESP32C3
#include <zephyr/drivers/interrupt_controller/intc_esp32.h> #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#else #else
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h> #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
@ -29,7 +29,7 @@ LOG_MODULE_REGISTER(esp32_spi, CONFIG_SPI_LOG_LEVEL);
#include "spi_context.h" #include "spi_context.h"
#include "spi_esp32_spim.h" #include "spi_esp32_spim.h"
#ifdef CONFIG_SOC_ESP32C3 #ifdef CONFIG_SOC_SERIES_ESP32C3
#define ISR_HANDLER isr_handler_t #define ISR_HANDLER isr_handler_t
#else #else
#define ISR_HANDLER intr_handler_t #define ISR_HANDLER intr_handler_t
@ -180,11 +180,11 @@ static int spi_esp32_init_dma(const struct device *dev)
#else #else
channel_offset = 1; channel_offset = 1;
#endif /* SOC_GDMA_SUPPORTED */ #endif /* SOC_GDMA_SUPPORTED */
#ifdef CONFIG_SOC_ESP32 #ifdef CONFIG_SOC_SERIES_ESP32
/*Connect SPI and DMA*/ /*Connect SPI and DMA*/
DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, cfg->dma_host + 1, DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, cfg->dma_host + 1,
((cfg->dma_host + 1) * 2)); ((cfg->dma_host + 1) * 2));
#endif /* CONFIG_SOC_ESP32 */ #endif /* CONFIG_SOC_SERIES_ESP32 */
data->hal_config.dma_in = (spi_dma_dev_t *)cfg->spi; data->hal_config.dma_in = (spi_dma_dev_t *)cfg->spi;
data->hal_config.dma_out = (spi_dma_dev_t *)cfg->spi; data->hal_config.dma_out = (spi_dma_dev_t *)cfg->spi;
@ -351,7 +351,7 @@ static int IRAM_ATTR spi_esp32_configure(const struct device *dev,
* Workaround for ESP32S3 and ESP32C3 SoC. This dummy transaction is needed to sync CLK and * Workaround for ESP32S3 and ESP32C3 SoC. This dummy transaction is needed to sync CLK and
* software controlled CS when SPI is in mode 3 * software controlled CS when SPI is in mode 3
*/ */
#if defined(CONFIG_SOC_ESP32S3) || defined(CONFIG_SOC_ESP32C3) #if defined(CONFIG_SOC_SERIES_ESP32S3) || defined(CONFIG_SOC_SERIES_ESP32C3)
if (ctx->num_cs_gpios && (hal_dev->mode & (SPI_MODE_CPOL | SPI_MODE_CPHA))) { if (ctx->num_cs_gpios && (hal_dev->mode & (SPI_MODE_CPOL | SPI_MODE_CPHA))) {
spi_esp32_transfer(dev); spi_esp32_transfer(dev);
} }
@ -463,7 +463,7 @@ static const struct spi_driver_api spi_api = {
.release = spi_esp32_release .release = spi_esp32_release
}; };
#ifdef CONFIG_SOC_ESP32 #ifdef CONFIG_SOC_SERIES_ESP32
#define GET_AS_CS(idx) .as_cs = DT_INST_PROP(idx, clk_as_cs), #define GET_AS_CS(idx) .as_cs = DT_INST_PROP(idx, clk_as_cs),
#else #else
#define GET_AS_CS(idx) #define GET_AS_CS(idx)

2
drivers/timer/Kconfig.esp32c3_sys
View file

@ -5,7 +5,7 @@
config ESP32C3_SYS_TIMER config ESP32C3_SYS_TIMER
bool "ESP32C3 sys-timer support" bool "ESP32C3 sys-timer support"
depends on SOC_ESP32C3 depends on SOC_SERIES_ESP32C3
default y default y
select TICKLESS_CAPABLE select TICKLESS_CAPABLE
select TIMER_HAS_64BIT_CYCLE_COUNTER select TIMER_HAS_64BIT_CYCLE_COUNTER

4
drivers/watchdog/wdt_esp32.c
View file

@ -15,7 +15,7 @@
#include <string.h> #include <string.h>
#include <zephyr/drivers/watchdog.h> #include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/clock_control.h> #include <zephyr/drivers/clock_control.h>
#ifndef CONFIG_SOC_ESP32C3 #ifndef CONFIG_SOC_SERIES_ESP32C3
#include <zephyr/drivers/interrupt_controller/intc_esp32.h> #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#else #else
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h> #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
@ -25,7 +25,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_esp32, CONFIG_WDT_LOG_LEVEL); LOG_MODULE_REGISTER(wdt_esp32, CONFIG_WDT_LOG_LEVEL);
#ifdef CONFIG_SOC_ESP32C3 #ifdef CONFIG_SOC_SERIES_ESP32C3
#define ISR_HANDLER isr_handler_t #define ISR_HANDLER isr_handler_t
#else #else
#define ISR_HANDLER intr_handler_t #define ISR_HANDLER intr_handler_t

2
modules/Kconfig.esp32
View file

@ -3,4 +3,4 @@
config HAS_ESPRESSIF_HAL config HAS_ESPRESSIF_HAL
bool bool
depends on SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3 || SOC_ESP32_NET || SOC_ESP32S3 depends on SOC_FAMILY_ESP32

2
samples/boards/esp32/flash_encryption/src/main.c
View file

@ -16,7 +16,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(flash_encryption, CONFIG_LOG_DEFAULT_LEVEL); LOG_MODULE_REGISTER(flash_encryption, CONFIG_LOG_DEFAULT_LEVEL);
#if !defined(CONFIG_SOC_ESP32) #if !defined(CONFIG_SOC_SERIES_ESP32)
#error Flash encryption feature is only available for ESP32 SOC yet. #error Flash encryption feature is only available for ESP32 SOC yet.
#endif #endif

54
soc/riscv/esp32c3/Kconfig.defconfig
View file

@ -1,54 +0,0 @@
# ESP32C3 board configuration
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_ESP32C3
if BOOTLOADER_MCUBOOT
config HAS_FLASH_LOAD_OFFSET
default y
config MCUBOOT_GENERATE_UNSIGNED_IMAGE
default y
config MCUBOOT_GENERATE_CONFIRMED_IMAGE
default y
config ROM_START_OFFSET
default 0x20
endif
config SOC
default "esp32c3"
config NUM_IRQS
default 62
config GEN_ISR_TABLES
default y
config GEN_SW_ISR_TABLE
default y
config GEN_IRQ_VECTOR_TABLE
default n
config DYNAMIC_INTERRUPTS
default y
config ISR_STACK_SIZE
default 2048
config ATOMIC_OPERATIONS_C
default y
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 16000000
endif

5
soc/riscv/espressif_esp32/CMakeLists.txt Normal file
View file

@ -0,0 +1,5 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(${SOC_SERIES})
add_subdirectory(common)

16
soc/riscv/espressif_esp32/Kconfig Normal file
View file

@ -0,0 +1,16 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_ESP32
bool
if SOC_FAMILY_ESP32
config SOC_FAMILY
string
default "espressif_esp32"
source "soc/riscv/espressif_esp32/common/Kconfig.soc"
source "soc/riscv/espressif_esp32/*/Kconfig.soc"
endif # SOC_FAMILY_ESP32

5
soc/riscv/espressif_esp32/Kconfig.defconfig Normal file
View file

@ -0,0 +1,5 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
source "soc/riscv/espressif_esp32/common/Kconfig.defconfig.series"
source "soc/riscv/espressif_esp32/*/Kconfig.defconfig.series"

4
soc/riscv/espressif_esp32/Kconfig.soc Normal file
View file

@ -0,0 +1,4 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
source "soc/riscv/espressif_esp32/*/Kconfig.series"

2
soc/riscv/espressif_esp32/common/CMakeLists.txt Normal file
View file

@ -0,0 +1,2 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0

52
soc/riscv/espressif_esp32/common/Kconfig.defconfig.series Normal file
View file

@ -0,0 +1,52 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_ESP32
config GEN_ISR_TABLES
default y
config GEN_SW_ISR_TABLE
default y
config GEN_IRQ_VECTOR_TABLE
default n
config DYNAMIC_INTERRUPTS
default y
config ISR_STACK_SIZE
default 2048
config ATOMIC_OPERATIONS_C
default y
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 16000000
config SYS_CLOCK_TICKS_PER_SEC
default 1000
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
config CLOCK_CONTROL
default y
if BOOTLOADER_MCUBOOT
config HAS_FLASH_LOAD_OFFSET
default y
config MCUBOOT_GENERATE_UNSIGNED_IMAGE
default y
config MCUBOOT_GENERATE_CONFIRMED_IMAGE
default y
config ROM_START_OFFSET
default 0x20
endif # BOOTLOADER_MCUBOOT config
endif # SOC_FAMILY_ESP32

15
soc/riscv/espressif_esp32/common/Kconfig.soc Normal file
View file

@ -0,0 +1,15 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_ESP32
config ESPTOOLPY_FLASHFREQ_80M
bool
config FLASH_SIZE
int
config FLASH_BASE_ADDRESS
hex
endif # SOC_FAMILY_ESP32

2
soc/riscv/esp32c3/CMakeLists.txt → soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt
View file

@ -39,7 +39,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
${CMAKE_COMMAND} -G${CMAKE_GENERATOR} ${CMAKE_COMMAND} -G${CMAKE_GENERATOR}
-S ${espidf_components_dir}/bootloader/subproject -S ${espidf_components_dir}/bootloader/subproject
-B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig
-DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES}
-DPYTHON_DEPS_CHECKED=1 -DPYTHON_DEPS_CHECKED=1
-DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER}
-DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}

21
soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series Normal file
View file

@ -0,0 +1,21 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_ESP32C3
config SOC_SERIES
default "esp32c3"
config NUM_IRQS
default 62
config ESPTOOLPY_FLASHFREQ_80M
default y
config FLASH_SIZE
default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
endif # SOC_SERIES_ESP32C3

20
soc/riscv/espressif_esp32/esp32c3/Kconfig.series Normal file
View file

@ -0,0 +1,20 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_ESP32C3
bool "ESP32C3"
select RISCV
select RISCV_GP
select DYNAMIC_INTERRUPTS
select CLOCK_CONTROL
select PINCTRL
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select HAS_ESPRESSIF_HAL
select SOC_FAMILY_ESP32
select XIP if !MCUBOOT
select HAS_PM
help
Enable support for Espressif ESP32-C3

52
soc/riscv/esp32c3/Kconfig.soc → soc/riscv/espressif_esp32/esp32c3/Kconfig.soc
View file

@ -1,42 +1,28 @@
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
config SOC_ESP32C3 if SOC_SERIES_ESP32C3
bool "ESP32C3"
select RISCV
select RISCV_GP
select DYNAMIC_INTERRUPTS
select CLOCK_CONTROL
select PINCTRL
select XIP if !MCUBOOT
select HAS_ESPRESSIF_HAL
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select HAS_PM
if SOC_ESP32C3
config SOC_FAMILY_ESP32
bool
default y
config IDF_TARGET_ESP32C3 config IDF_TARGET_ESP32C3
bool "ESP32C3 as target board" bool "ESP32C3 as target board"
default y default y
config ESPTOOLPY_FLASHFREQ_80M choice SOC_PART_NUMBER
bool prompt "ESP32-C3 SOC Selection"
default y depends on SOC_SERIES_ESP32C3
config FLASH_SIZE config SOC_ESP32C3
int bool "ESP32C3"
default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) config SOC_ESP32C3_FX4
bool "ESP32C3_FX4"
config SOC_ESP32C3_MINI_N4
bool "ESP32C3_MINI_N4"
config SOC_ESP32C3_WROOM_H2
bool "ESP32C3_MINI_N4"
config SOC_ESP32C3_WROOM_H4
bool "ESP32C3_MINI_N4"
config FLASH_BASE_ADDRESS endchoice # SOC_PART_NUMBER
hex
default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
config ESP_SYSTEM_RTC_EXT_XTAL config ESP_SYSTEM_RTC_EXT_XTAL
bool bool
@ -64,7 +50,7 @@ config ESP32C3_RTC_CLK_SRC_EXT_OSC
config ESP32C3_RTC_CLK_SRC_INT_8MD256 config ESP32C3_RTC_CLK_SRC_INT_8MD256
bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" bool "Internal 8MHz oscillator, divided by 256 (~32kHz)"
endchoice endchoice # ESP32C3_RTC_CLK_SRC
config ESP32C3_RTC_CLK_CAL_CYCLES config ESP32C3_RTC_CLK_CAL_CYCLES
int "Number of cycles for RTC_SLOW_CLK calibration" int "Number of cycles for RTC_SLOW_CLK calibration"
@ -102,7 +88,7 @@ config ESP32_PHY_MAX_TX_POWER
config MAC_BB_PD config MAC_BB_PD
bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
depends on SOC_ESP32C3 && TICKLESS_KERNEL depends on SOC_SERIES_ESP32C3 && TICKLESS_KERNEL
default n default n
help help
If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered
@ -110,4 +96,4 @@ config MAC_BB_PD
by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only), by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth). 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth).
endif endif # SOC_SERIES_ESP32C3

0
soc/riscv/esp32c3/default.ld → soc/riscv/espressif_esp32/esp32c3/default.ld
View file

0
soc/riscv/esp32c3/idle.c → soc/riscv/espressif_esp32/esp32c3/idle.c
View file

0
soc/riscv/esp32c3/linker.ld → soc/riscv/espressif_esp32/esp32c3/linker.ld
View file

2
soc/riscv/esp32c3/loader.c → soc/riscv/espressif_esp32/esp32c3/loader.c
View file

@ -18,7 +18,7 @@
#ifdef CONFIG_BOOTLOADER_MCUBOOT #ifdef CONFIG_BOOTLOADER_MCUBOOT
#define BOOT_LOG_INF(_fmt, ...) \ #define BOOT_LOG_INF(_fmt, ...) \
ets_printf("[" CONFIG_SOC "] [INF] " _fmt "\n\r", ##__VA_ARGS__) ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) #define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))

0
soc/riscv/esp32c3/mcuboot.ld → soc/riscv/espressif_esp32/esp32c3/mcuboot.ld
View file

0
soc/riscv/esp32c3/pinctrl_soc.h → soc/riscv/espressif_esp32/esp32c3/pinctrl_soc.h
View file

0
soc/riscv/esp32c3/power.c → soc/riscv/espressif_esp32/esp32c3/power.c
View file

0
soc/riscv/esp32c3/soc.c → soc/riscv/espressif_esp32/esp32c3/soc.c
View file

0
soc/riscv/esp32c3/soc.h → soc/riscv/espressif_esp32/esp32c3/soc.h
View file

0
soc/riscv/esp32c3/soc_irq.S → soc/riscv/espressif_esp32/esp32c3/soc_irq.S
View file

0
soc/riscv/esp32c3/soc_irq.c → soc/riscv/espressif_esp32/esp32c3/soc_irq.c
View file

0
soc/riscv/esp32c3/vectors.S → soc/riscv/espressif_esp32/esp32c3/vectors.S
View file

365
soc/xtensa/esp32/include/_soc_inthandlers.h
View file

@ -1,365 +0,0 @@
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int mask)
{
int irq;
if (mask & 0x7f) {
if (mask & 0x7) {
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
if (mask & BIT(2)) {
mask = BIT(2);
irq = 2;
goto handle_irq;
}
} else {
if (mask & 0x18) {
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(4)) {
mask = BIT(4);
irq = 4;
goto handle_irq;
}
} else {
if (mask & BIT(5)) {
mask = BIT(5);
irq = 5;
goto handle_irq;
}
if (mask & BIT(6)) {
mask = BIT(6);
irq = 6;
goto handle_irq;
}
}
}
} else {
if (mask & 0x780) {
if (mask & 0x180) {
if (mask & BIT(7)) {
mask = BIT(7);
irq = 7;
goto handle_irq;
}
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
} else {
if (mask & BIT(9)) {
mask = BIT(9);
irq = 9;
goto handle_irq;
}
if (mask & BIT(10)) {
mask = BIT(10);
irq = 10;
goto handle_irq;
}
}
} else {
if (mask & 0x3000) {
if (mask & BIT(12)) {
mask = BIT(12);
irq = 12;
goto handle_irq;
}
if (mask & BIT(13)) {
mask = BIT(13);
irq = 13;
goto handle_irq;
}
} else {
if (mask & BIT(17)) {
mask = BIT(17);
irq = 17;
goto handle_irq;
}
if (mask & BIT(18)) {
mask = BIT(18);
irq = 18;
goto handle_irq;
}
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int mask)
{
int irq;
if (mask & 0x408800) {
if (mask & BIT(11)) {
mask = BIT(11);
irq = 11;
goto handle_irq;
}
if (mask & BIT(15)) {
mask = BIT(15);
irq = 15;
goto handle_irq;
}
if (mask & BIT(22)) {
mask = BIT(22);
irq = 22;
goto handle_irq;
}
} else {
if (mask & BIT(23)) {
mask = BIT(23);
irq = 23;
goto handle_irq;
}
if (mask & BIT(27)) {
mask = BIT(27);
irq = 27;
goto handle_irq;
}
if (mask & BIT(29)) {
mask = BIT(29);
irq = 29;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int7(unsigned int mask)
{
int irq;
if (mask & BIT(14)) {
mask = BIT(14);
irq = 14;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int mask)
{
int irq;
if (mask & BIT(16)) {
mask = BIT(16);
irq = 16;
goto handle_irq;
}
if (mask & BIT(26)) {
mask = BIT(26);
irq = 26;
goto handle_irq;
}
if (mask & BIT(31)) {
mask = BIT(31);
irq = 31;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int mask)
{
int irq;
if (mask & BIT(19)) {
mask = BIT(19);
irq = 19;
goto handle_irq;
}
if (mask & BIT(20)) {
mask = BIT(20);
irq = 20;
goto handle_irq;
}
if (mask & BIT(21)) {
mask = BIT(21);
irq = 21;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int4(unsigned int mask)
{
int irq;
if (mask & 0x3000000) {
if (mask & BIT(24)) {
mask = BIT(24);
irq = 24;
goto handle_irq;
}
if (mask & BIT(25)) {
mask = BIT(25);
irq = 25;
goto handle_irq;
}
} else {
if (mask & BIT(28)) {
mask = BIT(28);
irq = 28;
goto handle_irq;
}
if (mask & BIT(30)) {
mask = BIT(30);
irq = 30;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int mask)
{
return 0;
}

55
soc/xtensa/esp32s2/Kconfig.defconfig
View file

@ -1,55 +0,0 @@
# ESP32S2 board configuration
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_ESP32S2
if BOOTLOADER_MCUBOOT
config HAS_FLASH_LOAD_OFFSET
default y
config MCUBOOT_GENERATE_UNSIGNED_IMAGE
default y
config MCUBOOT_GENERATE_CONFIRMED_IMAGE
default y
config ROM_START_OFFSET
default 0x20
endif
config SOC
default "esp32s2"
config SOC_TOOLCHAIN_NAME
string
default "espressif_esp32s2"
config GEN_ISR_TABLES
default y
config GEN_IRQ_VECTOR_TABLE
default n
config ISR_STACK_SIZE
default 2048
config HEAP_MEM_POOL_SIZE
default 32768
config MP_MAX_NUM_CPUS
default 1
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config XTENSA_CCOUNT_HZ
default SYS_CLOCK_HW_CYCLES_PER_SEC
endif

371
soc/xtensa/esp32s2/include/_soc_inthandlers.h
View file

@ -1,371 +0,0 @@
/*
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int mask)
{
int irq;
if (mask & 0x7f) {
if (mask & 0x7) {
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
if (mask & BIT(2)) {
mask = BIT(2);
irq = 2;
goto handle_irq;
}
} else {
if (mask & 0x18) {
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(4)) {
mask = BIT(4);
irq = 4;
goto handle_irq;
}
} else {
if (mask & BIT(5)) {
mask = BIT(5);
irq = 5;
goto handle_irq;
}
if (mask & BIT(6)) {
mask = BIT(6);
irq = 6;
goto handle_irq;
}
}
}
} else {
if (mask & 0x780) {
if (mask & 0x180) {
if (mask & BIT(7)) {
mask = BIT(7);
irq = 7;
goto handle_irq;
}
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
} else {
if (mask & BIT(9)) {
mask = BIT(9);
irq = 9;
goto handle_irq;
}
if (mask & BIT(10)) {
mask = BIT(10);
irq = 10;
goto handle_irq;
}
}
} else {
if (mask & 0x3000) {
if (mask & BIT(12)) {
mask = BIT(12);
irq = 12;
goto handle_irq;
}
if (mask & BIT(13)) {
mask = BIT(13);
irq = 13;
goto handle_irq;
}
} else {
if (mask & BIT(17)) {
mask = BIT(17);
irq = 17;
goto handle_irq;
}
if (mask & BIT(18)) {
mask = BIT(18);
irq = 18;
goto handle_irq;
}
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int mask)
{
int irq;
if (mask & 0x408800) {
if (mask & BIT(11)) {
mask = BIT(11);
irq = 11;
goto handle_irq;
}
if (mask & BIT(15)) {
mask = BIT(15);
irq = 15;
goto handle_irq;
}
if (mask & BIT(22)) {
mask = BIT(22);
irq = 22;
goto handle_irq;
}
} else {
if (mask & BIT(23)) {
mask = BIT(23);
irq = 23;
goto handle_irq;
}
if (mask & BIT(27)) {
mask = BIT(27);
irq = 27;
goto handle_irq;
}
if (mask & BIT(29)) {
mask = BIT(29);
irq = 29;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int7(unsigned int mask)
{
int irq;
if (mask & BIT(14)) {
mask = BIT(14);
irq = 14;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int mask)
{
int irq;
if (mask & BIT(16)) {
mask = BIT(16);
irq = 16;
goto handle_irq;
}
if (mask & BIT(26)) {
mask = BIT(26);
irq = 26;
goto handle_irq;
}
if (mask & BIT(31)) {
mask = BIT(31);
irq = 31;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int mask)
{
int irq;
if (mask & BIT(19)) {
mask = BIT(19);
irq = 19;
goto handle_irq;
}
if (mask & BIT(20)) {
mask = BIT(20);
irq = 20;
goto handle_irq;
}
if (mask & BIT(21)) {
mask = BIT(21);
irq = 21;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int4(unsigned int mask)
{
int irq;
if (mask & 0x3000000) {
if (mask & BIT(24)) {
mask = BIT(24);
irq = 24;
goto handle_irq;
}
if (mask & BIT(25)) {
mask = BIT(25);
irq = 25;
goto handle_irq;
}
} else {
if (mask & BIT(28)) {
mask = BIT(28);
irq = 28;
goto handle_irq;
}
if (mask & BIT(30)) {
mask = BIT(30);
irq = 30;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int mask)
{
return 0;
}

5
soc/xtensa/espressif_esp32/CMakeLists.txt Normal file
View file

@ -0,0 +1,5 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(${SOC_SERIES})
add_subdirectory(common)

16
soc/xtensa/espressif_esp32/Kconfig Normal file
View file

@ -0,0 +1,16 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_ESP32
bool
if SOC_FAMILY_ESP32
config SOC_FAMILY
string
default "espressif_esp32"
source "soc/xtensa/espressif_esp32/common/Kconfig.soc"
source "soc/xtensa/espressif_esp32/*/Kconfig.soc"
endif # SOC_FAMILY_ESP32

5
soc/xtensa/espressif_esp32/Kconfig.defconfig Normal file
View file

@ -0,0 +1,5 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
source "soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series"
source "soc/xtensa/espressif_esp32/*/Kconfig.defconfig.series"

4
soc/xtensa/espressif_esp32/Kconfig.soc Normal file
View file

@ -0,0 +1,4 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
source "soc/xtensa/espressif_esp32/*/Kconfig.series"

4
soc/xtensa/espressif_esp32/common/CMakeLists.txt Normal file
View file

@ -0,0 +1,4 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(include)

63
soc/xtensa/esp32s3/Kconfig.defconfig → soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series
View file

@ -1,41 +1,44 @@
# ESP32 board configuration # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
if SOC_ESP32S3 if SOC_FAMILY_ESP32
if BOOTLOADER_MCUBOOT # Xtensa default options for ESP32 family
config HAS_FLASH_LOAD_OFFSET config XTENSA_RESET_VECTOR
default y
config MCUBOOT_GENERATE_UNSIGNED_IMAGE
default y
config MCUBOOT_GENERATE_CONFIRMED_IMAGE
default y
config ROM_START_OFFSET
default 0x20
endif
config SOC
default "esp32s3"
config SOC_TOOLCHAIN_NAME
string
default "espressif_esp32s3"
config HEAP_MEM_POOL_SIZE
default 32768
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n default n
config XTENSA_USE_CORE_CRT1
default n
config GEN_ISR_TABLES
default y
config GEN_IRQ_VECTOR_TABLE
default n
config CLOCK_CONTROL
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config XTENSA_CCOUNT_HZ config XTENSA_CCOUNT_HZ
default SYS_CLOCK_HW_CYCLES_PER_SEC default SYS_CLOCK_HW_CYCLES_PER_SEC
endif config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
if BOOTLOADER_MCUBOOT
config HAS_FLASH_LOAD_OFFSET
default y
config MCUBOOT_GENERATE_UNSIGNED_IMAGE
default y
config MCUBOOT_GENERATE_CONFIRMED_IMAGE
default y
config ROM_START_OFFSET
default 0x20
endif # BOOTLOADER_MCUBOOT
endif # SOC_FAMILY_ESP32

194
soc/xtensa/espressif_esp32/common/Kconfig.soc Normal file
View file

@ -0,0 +1,194 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_ESP32
config ESPTOOLPY_FLASHFREQ_80M
bool
config FLASH_SIZE
int
config FLASH_BASE_ADDRESS
hex
config ESP_SPIRAM
bool "Support for external, SPI-connected RAM"
help
This enables support for an external SPI RAM chip, connected in
parallel with the main SPI flash chip.
config ESP_HEAP_MIN_EXTRAM_THRESHOLD
int "Minimum threshold for external RAM allocation"
default 8192
range 1024 131072
depends on ESP_SPIRAM
help
Threshold to decide if memory will be allocated from DRAM
or SPIRAM. If value of allocation size is less than this value,
memory will be allocated from internal RAM.
config ESP_HEAP_SEARCH_ALL_REGIONS
bool "Search for all available heap regions"
depends on ESP_SPIRAM
default y
help
This configuration enables searching all available heap
regions. If the region of desired capability is exhausted,
memory will be allocated from other available region.
menu "SPI RAM config"
depends on ESP_SPIRAM
choice SPIRAM_TYPE
prompt "Type of SPI RAM chip in use"
depends on ESP_SPIRAM
default SPIRAM_TYPE_ESPPSRAM16
config SPIRAM_TYPE_ESPPSRAM16
bool "ESP-PSRAM16 or APS1604"
config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32 or IS25WP032"
config SPIRAM_TYPE_ESPPSRAM64
bool "ESP-PSRAM64 or LY68L6400"
endchoice # SPIRAM_TYPE
config ESP_SPIRAM_SIZE
int "Size of SPIRAM part"
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
help
Specify size of SPIRAM part.
NOTE: If SPIRAM size is greater than 4MB, only
lower 4MB can be allocated using k_malloc().
choice SPIRAM_SPEED
prompt "Set RAM clock speed"
default SPIRAM_SPEED_40M
help
Select the speed for the SPI RAM chip.
If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
1. Flash SPI running at 40MHz and RAM SPI running at 40MHz
2. Flash SPI running at 80MHz and RAM SPI running at 40MHz
3. Flash SPI running at 80MHz and RAM SPI running at 80MHz
Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
will be occupied by the system. Which SPI host to use can be selected by the config item
SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
(ESPTOOLPY_FLASHFREQ_79M is true)
config SPIRAM_SPEED_26M
bool "26MHz clock speed"
depends on SOC_SERIES_ESP32S2
config SPIRAM_SPEED_20M
bool "20MHz clock speed"
depends on SOC_SERIES_ESP32S2
config SPIRAM_SPEED_40M
bool "40MHz clock speed"
config SPIRAM_SPEED_80M
depends on ESPTOOLPY_FLASHFREQ_80M
bool "80MHz clock speed"
endchoice # SPIRAM_SPEED
menu "PSRAM clock and cs IO for ESP32-DOWD"
config D0WD_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 17
help
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
config D0WD_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 16
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu # PSRAM clock and cs IO for ESP32-DOWD
menu "PSRAM clock and cs IO for ESP32-D2WD"
config D2WD_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 9
help
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
config D2WD_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 10
help
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu # PSRAM clock and cs IO for ESP32-D2WD
menu "PSRAM clock and cs IO for ESP32-PICO"
config PICO_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 10
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
IO.
For the reference hardware design, please refer to
https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
endmenu # PSRAM clock and cs IO for ESP32-PICO
config SPIRAM_CUSTOM_SPIWP_SD3_PIN
bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5
default n
help
This setting is only used if the SPI flash pins have been overridden by setting the eFuses
SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
mode, so a WP pin setting is necessary.
If this config item is set to N (default), the correct WP pin will be automatically used for any
Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
to Y and specify the GPIO number connected to the WP pin.
When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
configured in the bootloader.
config SPIRAM_SPIWP_SD3_PIN
int "Custom SPI PSRAM WP(SD3) Pin"
range 0 33
default 7
help
The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
value to the GPIO number of the SPIRAM WP pin.
config SPIRAM
bool
default y
endmenu # SPI RAM config
endif # SOC_FAMILY_ESP32

2
soc/xtensa/esp32s3/include/_soc_inthandlers.h → soc/xtensa/espressif_esp32/common/include/_soc_inthandlers.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

0
soc/xtensa/esp32/include/gdbstub/soc.h → soc/xtensa/espressif_esp32/common/include/gdbstub/soc.h
View file

2
soc/xtensa/esp32/CMakeLists.txt → soc/xtensa/espressif_esp32/esp32/CMakeLists.txt
View file

@ -40,7 +40,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
${CMAKE_COMMAND} -G${CMAKE_GENERATOR} ${CMAKE_COMMAND} -G${CMAKE_GENERATOR}
-S ${espidf_components_dir}/bootloader/subproject -S ${espidf_components_dir}/bootloader/subproject
-B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig
-DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES}
-DPYTHON_DEPS_CHECKED=1 -DPYTHON_DEPS_CHECKED=1
-DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER}
-DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}

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