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boards: st: stm32N6 boards xspi-nor-flash DTS configuration

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This PR defines the "st,stm32-xspi-nor" compatible Node
and the "st,stm32-xspi-psram" compatible Node
in conformance to the DTS specifications
Includes the size property (in Bits) of the external memory device

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2025-04-15 12:07:15 +02:00 • committed by Benjamin Cabé
commit 6b574e6d37
2 changed files with 9 additions and 6 deletions
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5
boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi
View file

@ -235,9 +235,10 @@ zephyr_udc0: &usbotg_hs1 {
<&rcc STM32_CLOCK(AHB5, 13)>;
status = "okay";
mx25um51245g: ospi-nor-flash@70000000 {
mx25um51245g: ospi-nor-flash@0 {
compatible = "st,stm32-xspi-nor";
reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */
reg = <0>;
size = <DT_SIZE_M(512)>; /* 512 Mbits */
ospi-max-frequency = <DT_FREQ_M(200)>;
spi-bus-width = <XSPI_OCTO_MODE>;
data-rate = <XSPI_DTR_TRANSFER>;

10
boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
View file

@ -250,9 +250,10 @@ zephyr_udc0: &usbotg_hs1 {
<&rcc STM32_CLOCK(AHB5, 13)>;
status = "okay";
memc: aps256xxn_obr: memory@90000000 {
memc: aps256xxn_obr: memory@0 {
compatible = "st,stm32-xspi-psram";
reg = <0x90000000 DT_SIZE_M(32)>; /* 256 Mbits */
reg = <0>;
size = <DT_SIZE_M(256)>; /* 256 Mbits */
fixed-latency;
io-x16-mode;
read-latency = <4>;
@ -273,9 +274,10 @@ zephyr_udc0: &usbotg_hs1 {
<&rcc STM32_CLOCK(AHB5, 13)>;
status = "okay";
mx66uw1g45g: ospi-nor-flash@70000000 {
mx66uw1g45g: ospi-nor-flash@0 {
compatible = "st,stm32-xspi-nor";
reg = <0x70000000 DT_SIZE_M(128)>; /* 1 Gbits */
reg = <0>;
size = <DT_SIZE_M(1024)>; /* 1Gbits */
ospi-max-frequency = <DT_FREQ_M(200)>;
spi-bus-width = <XSPI_OCTO_MODE>;
data-rate = <XSPI_DTR_TRANSFER>;