diff --git a/dts/arm/adi/max32/max32666-pinctrl.dtsi b/dts/arm/adi/max32/max32666-pinctrl.dtsi
new file mode 100644
index 00000000000..a44553f74a0
--- /dev/null
+++ b/dts/arm/adi/max32/max32666-pinctrl.dtsi
@@ -0,0 +1,646 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40008000 {
+
+			/omit-if-no-ref/ spixf_ss0_p0_0: spixf_ss0_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart2_cts_p0_0: uart2_cts_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr0_p0_0: tmr0_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixf_mosi_p0_1: spixf_mosi_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart2_tx_p0_1: uart2_tx_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr1_p0_1: tmr1_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixf_miso_p0_2: spixf_miso_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart2_rx_p0_2: uart2_rx_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr2_p0_2: tmr2_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixf_sck_p0_3: spixf_sck_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart2_rts_p0_3: uart2_rts_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr3_p0_3: tmr3_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio2_p0_4: spixf_sdio2_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p0_4: owm_io_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr4_p0_4: tmr4_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio3_p0_5: spixf_sdio3_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/owm_pe_p0_5: owm_pe_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr5_p0_5: tmr5_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2c0_scl_p0_6: i2c0_scl_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ swdio2_p0_6: swdio2_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr0_p0_6: tmr0_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2c0_sda_p0_7: i2c0_sda_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ swclk2_p0_7: swclck2_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr1_p0_7: tmr1_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixr_ss0_p0_8: spixr_ss0_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss0_p0_8: spi0_ss0_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0_cts_p0_8: uart0_cts_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr2_p0_8: tmr2_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixr_mosi_p0_9: spixr_mosi_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_mosi_p0_9: spi0_mosi_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0_tx_p0_9: uart0_tx_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr3_p0_9: tmr3_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixr_miso_p0_10: spixr_miso_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_miso_p0_10: spi0_miso_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0_rx_p0_10: uart0_rx_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr4_p0_10: tmr4_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixr_sck_p0_11: spixr_sck_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_sck_p0_11: spi0_sck_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0_rts_p0_11: uart0_rts_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr5_p0_11: tmr5_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio2_p0_12: spixr_sdio2_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_sdio2_p0_12: spi0_sdio2_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p0_12: owm_io_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr0_p0_12: tmr0_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio3_p0_13: spixr_sdio3_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_sdio3_p0_13: spi0_sdio3_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_pe_p0_13: owm_pe_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr1_p0_13: tmr1_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_p0_14: i2c1_scl_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss1_p0_14: spi0_ss1_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2_p0_14: tmr2_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_p0_15: i2c1_sda_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss2_p0_15: spi0_ss2_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3_p0_15: tmr3_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF4)>;
+			};
+
+			/omit-if-no-ref/ ain0n_p0_16: ain0n_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p0_16: spi1_ss0_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p0_16: owm_io_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr4_p0_16: tmr4_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF4)>;
+			};
+
+			/omit-if-no-ref/ ain0p_p0_17: ain0p_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_p0_17: spi1_mosi_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_pe_p0_17: owm_pe_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr5_p0_17: tmr5_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF4)>;
+			};
+
+			/omit-if-no-ref/ ain1n_p0_18: ain1n_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_miso_p0_18: spi1_miso_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0_p0_18: tmr0_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF4)>;
+			};
+
+			/omit-if-no-ref/ ain1p_p0_19: ain1p_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_sck_p0_19: spi1_sck_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1_p0_19: tmr1_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF4)>;
+			};
+
+			/omit-if-no-ref/ ain2n_p0_20: ain2n_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_sdio2_p0_20: spi1_sdio2_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p0_20: uart1_rx_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr2_p0_20: tmr2_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF4)>;
+			};
+
+			/omit-if-no-ref/ ain2p_p0_21: ain2p_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_sdio3_p0_21: spi1_sdio3_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p0_21: uart1_tx_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr3_p0_21: tmr3_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF4)>;
+			};
+
+			/omit-if-no-ref/ ain3n_p0_22: ain3n_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss1_p0_22: spi1_ss1_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_cts_p0_22: uart1_cts_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr4_p0_22: tmr4_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF4)>;
+			};
+
+			/omit-if-no-ref/ ain3p_p0_23: ain3p_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss2_p0_23: spi1_ss2_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rts_p0_23: uart1_rts_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr5_p0_23: tmr5_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF4)>;
+			};
+
+			/omit-if-no-ref/ pcm_lrclk_p0_24: pcm_lrclk_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2_ss0_p0_24: spi2_ss0_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p0_24: owm_io_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr0_p0_24: tmr0_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF4)>;
+			};
+
+			/omit-if-no-ref/ pcm_dout_p0_25: pcm_dout_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_p0_25: spi2_mosi_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_pe_p0_25: owm_pe_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr1_p0_25: tmr1_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF4)>;
+			};
+
+			/omit-if-no-ref/ pcm_din_p0_26: pcm_din_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2_miso_p0_26: spi2_miso_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2_p0_26: tmr2_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF4)>;
+			};
+
+			/omit-if-no-ref/ pcm_bclk_p0_27: pcm_bclk_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2_sck_p0_27: spi2_sck_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3_p0_27: tmr3_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF4)>;
+			};
+
+			/omit-if-no-ref/ pdm_data2_p0_28: pdm_data2_p0_28 {
+				pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2_sdio2_p0_28: spi2_sdio2_p0_28 {
+				pinmux = <MAX32_PINMUX(0, 28, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_rx_p0_28: uart2_rx_p0_28 {
+				pinmux = <MAX32_PINMUX(0, 28, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr4_p0_28: tmr4_p0_28 {
+				pinmux = <MAX32_PINMUX(0, 28, AF4)>;
+			};
+
+			/omit-if-no-ref/ pdm_data3_p0_29: pdm_data3_p0_29 {
+				pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2_sdio3_p0_29: spi2_sdio3_p0_29 {
+				pinmux = <MAX32_PINMUX(0, 29, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_tx_p0_29: uart2_tx_p0_29 {
+				pinmux = <MAX32_PINMUX(0, 29, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr5_p0_29: tmr5_p0_29 {
+				pinmux = <MAX32_PINMUX(0, 29, AF4)>;
+			};
+
+			/omit-if-no-ref/ pdm_rx_clk_p0_30: pdm_rx_clk_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2_ss1_p0_30: spi2_ss1_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_cts_p0_30: uart2_cts_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr0_p0_30: tmr0_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF4)>;
+			};
+
+			/omit-if-no-ref/ pdm_mclk_p0_31: pdm_mclk_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2_ss2_p0_31: spi2_ss2_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_rts_p0_31: uart2_rts_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr1_p0_31: tmr1_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF4)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat3_p1_0: sdhc_dat3_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ sdma_tms_p1_0: sdma_tms_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt0_p1_0: pt0_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ sdhc_cmd_p1_1: sdhc_cmd_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ sdma_tdo_p1_1: sdma_tdo_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt1_p1_1: pt1_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat0_p1_2: sdhc_dat0_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ sdma_tdi_p1_2: sdma_tdi_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt2_p1_2: pt2_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ sdhc_clk_p1_3: sdhc_clk_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ sdma_tck_p1_3: sdma_tck_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt3_p1_3: pt3_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF4)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat1_p1_4: sdhc_dat1_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_rx_p1_4: uart0_rx_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt5_p1_4: pt5_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF4)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat2_p1_5: sdhc_dat2_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_tx_p1_5: uart0_tx_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt5_p1_5: pt5_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF4)>;
+			};
+
+			/omit-if-no-ref/ sdhc_wp_p1_6: sdhc_wp_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_cts_p1_6: uart0_cts_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt6_p1_6: pt6_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ sdhc_cdn_p1_7: sdhc_cdn_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_rts_p1_7: uart0_rts_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt7_p1_7: pt7_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss0_p1_8: spi0_ss0_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt8_p1_8: pt8_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ spi0_mosi_p1_9: spi0_mosi_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt9_p1_9: pt9_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF4)>;
+			};
+
+			/omit-if-no-ref/ spi0_miso_p1_10: spi0_miso_p1_10 {
+				pinmux = <MAX32_PINMUX(1, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt10_p1_10: pt10_p1_10 {
+				pinmux = <MAX32_PINMUX(1, 10, AF4)>;
+			};
+
+			/omit-if-no-ref/ spi0_sck_p1_11: spi0_sck_p1_11 {
+				pinmux = <MAX32_PINMUX(1, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt11_p1_11: pt11_p1_11 {
+				pinmux = <MAX32_PINMUX(1, 11, AF4)>;
+			};
+
+			/omit-if-no-ref/ spi0_sdio2_p1_12: spi0_sdio2_p1_12 {
+				pinmux = <MAX32_PINMUX(1, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p1_12: uart1_rx_p1_12 {
+				pinmux = <MAX32_PINMUX(1, 12, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt12_p1_12: pt12_p1_12 {
+				pinmux = <MAX32_PINMUX(1, 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ spi0_sdio3_p1_13: spi0_sdio3_p1_13 {
+				pinmux = <MAX32_PINMUX(1, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p1_13: uart1_tx_p1_13 {
+				pinmux = <MAX32_PINMUX(1, 13, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt13_p1_13: pt13_p1_13 {
+				pinmux = <MAX32_PINMUX(1, 13, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_p1_14: i2c2_scl_p1_14 {
+				pinmux = <MAX32_PINMUX(1, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_cts_p1_14: uart1_cts_p1_14 {
+				pinmux = <MAX32_PINMUX(1, 14, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt14_p1_14: pt14_p1_14 {
+				pinmux = <MAX32_PINMUX(1, 14, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_p1_15: i2c2_sda_p1_15 {
+				pinmux = <MAX32_PINMUX(1, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_rts_p1_15: uart1_rts_p1_15 {
+				pinmux = <MAX32_PINMUX(1, 15, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt15_p1_15: pt15_p1_15 {
+				pinmux = <MAX32_PINMUX(1, 15, AF4)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/adi/max32/max32666.dtsi b/dts/arm/adi/max32/max32666.dtsi
new file mode 100644
index 00000000000..e9fd4bc9b67
--- /dev/null
+++ b/dts/arm/adi/max32/max32666.dtsi
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <adi/max32/max32xxx.dtsi>
+
+&clk_ipo {
+	clock-frequency = <DT_FREQ_M(96)>;
+};
+
+&uart0 {
+	/delete-property/ clock-source;
+};
+
+&uart1 {
+	/delete-property/ clock-source;
+};
+
+&uart2 {
+	/delete-property/ clock-source;
+};
+
+/* MAX32666 extra peripherals. */
+/ {
+	soc {
+		sram1: memory@20008000 {
+			compatible = "mmio-sram";
+			reg = <0x20008000 DT_SIZE_K(32)>;
+		};
+
+		sram2: memory@20010000 {
+			compatible = "mmio-sram";
+			reg = <0x20010000 DT_SIZE_K(64)>;
+		};
+
+		sram3: memory@20020000 {
+			compatible = "mmio-sram";
+			reg = <0x20020000 DT_SIZE_K(64)>;
+		};
+
+		sram4: memory@20030000 {
+			compatible = "mmio-sram";
+			reg = <0x20030000 DT_SIZE_K(128)>;
+		};
+
+		sram5: memory@20050000 {
+			compatible = "mmio-sram";
+			reg = <0x20050000 DT_SIZE_K(128)>;
+		};
+
+		sram6: memory@20070000 {
+			compatible = "mmio-sram";
+			reg = <0x20070000 DT_SIZE_K(8)>;
+		};
+
+		sram7: memory@20072000 {
+			compatible = "mmio-sram";
+			reg = <0x20072000 DT_SIZE_K(8)>;
+		};
+
+		sram8: memory@20074000 {
+			compatible = "mmio-sram";
+			reg = <0x20074000 DT_SIZE_K(16)>;
+		};
+
+		sram9: memory@20078000 {
+			compatible = "mmio-sram";
+			reg = <0x20078000 DT_SIZE_K(16)>;
+		};
+
+		sram10: memory@2007c000 {
+			compatible = "mmio-sram";
+			reg = <0x2007c000 DT_SIZE_K(32)>;
+		};
+
+		sram11: memory@20084000 {
+			compatible = "mmio-sram";
+			reg = <0x20084000 DT_SIZE_K(32)>;
+		};
+
+		flc1: flash_controller@40029400 {
+			compatible = "adi,max32-flash-controller";
+			reg = <0x40029400 0x400>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
+
+			flash1: flash@10080000 {
+				compatible = "soc-nv-flash";
+				reg = <0x10080000 DT_SIZE_K(512)>;
+				write-block-size = <16>;
+				erase-block-size = <8192>;
+			};
+		};
+	};
+};
diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig
index ff597b95cc8..80642dc3399 100644
--- a/soc/adi/max32/Kconfig
+++ b/soc/adi/max32/Kconfig
@@ -17,6 +17,9 @@ config SOC_MAX32655
 config SOC_MAX32662
 	select CPU_CORTEX_M4
 
+config SOC_MAX32666
+	select CPU_CORTEX_M4
+
 config SOC_MAX32670
 	select CPU_CORTEX_M4
 
diff --git a/soc/adi/max32/Kconfig.defconfig.max32666 b/soc/adi/max32/Kconfig.defconfig.max32666
new file mode 100644
index 00000000000..25213269dbc
--- /dev/null
+++ b/soc/adi/max32/Kconfig.defconfig.max32666
@@ -0,0 +1,14 @@
+# Analog Devices MAX32666 MCU
+
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MAX32666
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
+
+config NUM_IRQS
+	default 95
+
+endif # SOC_MAX32666
diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc
index d1db3d161b0..e56456047fb 100644
--- a/soc/adi/max32/Kconfig.soc
+++ b/soc/adi/max32/Kconfig.soc
@@ -21,6 +21,14 @@ config SOC_MAX32662
 	bool
 	select SOC_FAMILY_MAX32
 
+config SOC_MAX32666
+	bool
+	select SOC_FAMILY_MAX32
+
+config SOC_MAX32666_CPU0
+	bool
+	select SOC_MAX32666
+
 config SOC_MAX32670
 	bool
 	select SOC_FAMILY_MAX32
@@ -52,6 +60,7 @@ config SOC_MAX32690_M4
 config SOC
 	default "max32655" if SOC_MAX32655
 	default "max32662" if SOC_MAX32662
+	default "max32666" if SOC_MAX32666
 	default "max32670" if SOC_MAX32670
 	default "max32672" if SOC_MAX32672
 	default "max32675" if SOC_MAX32675
diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml
index e8f36ee2d4c..701509dc15c 100644
--- a/soc/adi/max32/soc.yml
+++ b/soc/adi/max32/soc.yml
@@ -8,6 +8,9 @@ family:
     cpuclusters:
     - name: m4
   - name: max32662
+  - name: max32666
+    cpuclusters:
+    - name: cpu0
   - name: max32670
   - name: max32672
   - name: max32675