Microchip: MEC172x Add aggregated interrupt driver
Add driver implementation and header files for a MEC172x aggregated interrupt driver. Enable the parent(ECIA) node to have the driver initialize interrupt hardware for use. Enable child nodes for those GIRQs used for aggregation. Refer to chip documention for the list of GIRQs restricted to aggregation and those which support direct mode. Add chip level device tree node for MEC172x EC interrupt aggregator parent and GIRQ children. Each child node contains a list of sources representing the source bit position in the GIRQ registers. Add DT bindings for ECIA and GIRQ nodes. Add build file(s) and configuration items for the MEC172x ECIA aggregated interrupt driver. Add and enable the MEC172x interrupt driver on the MEC172x evaluation board(EVB). Enable parent node to initialize ECIA hardware. Child nodes are left disabled until a future driver needs them. Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley
Christopher Friedt
parent
d5af33eaf0
commit
6b3749d2ff
11 changed files with 948 additions and 3 deletions
512
drivers/interrupt_controller/intc_mchp_ecia_xec.c
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512
drivers/interrupt_controller/intc_mchp_ecia_xec.c
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/*
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* Copyright (c) 2021 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for External interrupt controller in Microchip XEC devices
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*
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* Driver is currently implemented to support MEC172x ECIA GIRQs
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*/
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#define DT_DRV_COMPAT microchip_xec_ecia
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#include <arch/cpu.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#include <device.h>
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#include <soc.h>
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#include <sys/__assert.h>
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#include <drivers/clock_control/mchp_xec_clock_control.h>
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#include <drivers/interrupt_controller/intc_mchp_xec_ecia.h>
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/* defined at the SoC layer */
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#define MCHP_FIRST_GIRQ MCHP_FIRST_GIRQ_NOS
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#define MCHP_LAST_GIRQ MCHP_LAST_GIRQ_NOS
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#define MCHP_XEC_DIRECT_CAPABLE MCHP_ECIA_DIRECT_BITMAP
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#define GIRQ_ID_TO_BITPOS(id) ((id) + 8)
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/*
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* MEC SoC's have one and only one instance of ECIA. GIRQ8 register are located
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* at the beginning of the ECIA block.
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*/
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#define ECIA_XEC_REG_BASE \
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((struct ecia_regs *)(DT_REG_ADDR(DT_NODELABEL(ecia))))
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#define ECS_XEC_REG_BASE \
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((struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs))))
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#define PCR_XEC_REG_BASE \
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((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
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#define ECIA_XEC_PCR_REG_IDX DT_INST_CLOCKS_CELL(0, regidx)
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#define ECIA_XEC_PCR_BITPOS DT_INST_CLOCKS_CELL(0, bitpos)
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#define ECIA_XEC_PCR_INFO \
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MCHP_XEC_PCR_SCR_ENCODE(DT_INST_CLOCKS_CELL(0, regidx), \
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DT_INST_CLOCKS_CELL(0, bitpos))
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struct xec_girq_config {
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uintptr_t base;
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uint8_t girq_id;
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uint8_t num_srcs;
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uint8_t sources[32];
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};
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struct xec_ecia_config {
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uintptr_t ecia_base;
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struct mchp_xec_pcr_clk_ctrl clk_ctrl;
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const struct device *girq_node_handles[32];
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};
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struct xec_girq_src_data {
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mchp_xec_ecia_callback_t cb;
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void *data;
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};
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#define DEV_ECIA_CFG(ecia_dev) \
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((const struct xec_ecia_config *const)(ecia_dev)->config)
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#define DEV_GIRQ_CFG(girq_dev) \
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((const struct xec_girq_config *const)(girq_dev)->config)
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#define DEV_GIRQ_DATA(girq_dev) \
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((struct xec_girq_src_data *const)(girq_dev)->data)
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/*
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* Enable/disable specified GIRQ's aggregated output. Aggrated output is the
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* bit-wise or of all the GIRQ's result bits.
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*/
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void mchp_xec_ecia_girq_aggr_en(uint8_t girq_num, uint8_t enable)
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{
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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if (enable) {
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regs->BLK_EN_SET = BIT(girq_num);
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} else {
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regs->BLK_EN_CLR = BIT(girq_num);
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}
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}
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void mchp_xec_ecia_girq_src_clr(uint8_t girq_num, uint8_t src_bit_pos)
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{
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if ((girq_num < MCHP_FIRST_GIRQ) || (girq_num > MCHP_LAST_GIRQ)) {
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return;
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}
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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/* write 1 to clear */
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regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = BIT(src_bit_pos);
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}
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void mchp_xec_ecia_girq_src_en(uint8_t girq_num, uint8_t src_bit_pos)
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{
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if ((girq_num < MCHP_FIRST_GIRQ) || (girq_num > MCHP_LAST_GIRQ)) {
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return;
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}
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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/* write 1 to set */
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regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_SET = BIT(src_bit_pos);
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}
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void mchp_xec_ecia_girq_src_dis(uint8_t girq_num, uint8_t src_bit_pos)
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{
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if ((girq_num < MCHP_FIRST_GIRQ) || (girq_num > MCHP_LAST_GIRQ)) {
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return;
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}
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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/* write 1 to clear */
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regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_CLR = BIT(src_bit_pos);
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}
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void mchp_xec_ecia_girq_src_clr_bitmap(uint8_t girq_num, uint32_t bitmap)
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{
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if ((girq_num < MCHP_FIRST_GIRQ) || (girq_num > MCHP_LAST_GIRQ)) {
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return;
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}
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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/* write 1 to clear */
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regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = bitmap;
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}
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void mchp_xec_ecia_girq_src_en_bitmap(uint8_t girq_num, uint32_t bitmap)
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{
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if ((girq_num < MCHP_FIRST_GIRQ) || (girq_num > MCHP_LAST_GIRQ)) {
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return;
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}
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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/* write 1 to clear */
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regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_SET = bitmap;
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}
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void mchp_xec_ecia_girq_src_dis_bitmap(uint8_t girq_num, uint32_t bitmap)
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{
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if ((girq_num < MCHP_FIRST_GIRQ) || (girq_num > MCHP_LAST_GIRQ)) {
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return;
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}
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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/* write 1 to clear */
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regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_CLR = bitmap;
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}
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/*
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* Return read-only GIRQ result register. Result is bit-wise and of source
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* and enable registers.
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*/
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uint32_t mchp_xec_ecia_girq_result(uint8_t girq_num)
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{
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if ((girq_num < MCHP_FIRST_GIRQ) || (girq_num > MCHP_LAST_GIRQ)) {
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return 0U;
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}
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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return regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].RESULT;
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}
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/* Clear NVIC pending given the external NVIC input number (zero based) */
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void mchp_xec_ecia_nvic_clr_pend(uint32_t nvic_num)
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{
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if (nvic_num >= ((SCnSCB->ICTR + 1) * 32)) {
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return;
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}
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NVIC_ClearPendingIRQ(nvic_num);
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}
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/**
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* @brief enable GIRQn interrupt for specific source
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*
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* @param girq is the GIRQ number (8 - 26)
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* @param src is the interrupt source in the GIRQ (0 - 31)
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*/
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int mchp_xec_ecia_enable(int girq, int src)
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{
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if ((girq < MCHP_FIRST_GIRQ) || (girq > MCHP_LAST_GIRQ) ||
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(src < 0) || (src > 31)) {
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return -EINVAL;
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}
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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/* write 1 to set */
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regs->GIRQ[girq - MCHP_FIRST_GIRQ].EN_SET = BIT(src);
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return 0;
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}
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/**
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* @brief disable EXTI interrupt for specific line
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*
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* @param girq is the GIRQ number (8 - 26)
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* @param src is the interrupt source in the GIRQ (0 - 31)
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*/
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int mchp_xec_ecia_disable(int girq, int src)
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{
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if ((girq < MCHP_FIRST_GIRQ) || (girq > MCHP_LAST_GIRQ) ||
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(src < 0) || (src > 31)) {
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return -EINVAL;
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}
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struct ecia_regs *regs = ECIA_XEC_REG_BASE;
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/* write 1 to clear */
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regs->GIRQ[girq - MCHP_FIRST_GIRQ].EN_CLR = BIT(src);
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return 0;
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}
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/* forward reference */
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static const struct device *get_girq_dev(int girq_num);
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/**
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* @brief set GIRQn interrupt source callback
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*
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* @param dev_girq is the GIRQn device handle
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* @param src is the interrupt source in the GIRQ (0 - 31)
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* @param cb user callback
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* @param data user data
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*/
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int mchp_xec_ecia_set_callback_by_dev(const struct device *dev_girq, int src,
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mchp_xec_ecia_callback_t cb, void *data)
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{
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if ((dev_girq == NULL) || (src < 0) || (src > 31)) {
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return -EINVAL;
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}
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const struct xec_girq_config *const cfg = DEV_GIRQ_CFG(dev_girq);
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struct xec_girq_src_data *girq_data = DEV_GIRQ_DATA(dev_girq);
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/* source exists in this GIRQ? */
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if (!(cfg->sources[src] & BIT(7))) {
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return -EINVAL;
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}
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/* obtain the callback array index for the source */
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int idx = (int)(cfg->sources[src] & ~BIT(7));
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girq_data[idx].cb = cb;
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girq_data[idx].data = data;
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return 0;
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}
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/**
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* @brief set GIRQn interrupt source callback
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*
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* @param girq is the GIRQ number (8 - 26)
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* @param src is the interrupt source in the GIRQ (0 - 31)
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* @param cb user callback
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* @param data user data
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*/
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int mchp_xec_ecia_set_callback(int girq_num, int src,
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mchp_xec_ecia_callback_t cb, void *data)
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{
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const struct device *dev = get_girq_dev(girq_num);
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return mchp_xec_ecia_set_callback_by_dev(dev, src, cb, data);
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}
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/**
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* @brief unset GIRQn interrupt source callback by device handle
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*
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* @param dev_girq is the GIRQn device handle
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* @param src is the interrupt source in the GIRQ (0 - 31)
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*/
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int mchp_ecia_unset_callback_by_dev(const struct device *dev_girq, int src)
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{
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if ((dev_girq == NULL) || (src < 0) || (src > 31)) {
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return -EINVAL;
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}
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const struct xec_girq_config *const cfg = DEV_GIRQ_CFG(dev_girq);
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struct xec_girq_src_data *girq_data = DEV_GIRQ_DATA(dev_girq);
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/* source exists in this GIRQ? */
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if (!(cfg->sources[src] & BIT(7))) {
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return -EINVAL;
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}
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/* obtain the callback array index for the source */
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int idx = (int)(cfg->sources[src] & ~BIT(7));
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girq_data[idx].cb = NULL;
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girq_data[idx].data = NULL;
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return 0;
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}
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/**
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* @brief unset GIRQn interrupt source callback
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*
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* @param girq is the GIRQ number (8 - 26)
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* @param src is the interrupt source in the GIRQ (0 - 31)
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*/
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int mchp_ecia_unset_callback(int girq_num, int src)
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{
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const struct device *dev = get_girq_dev(girq_num);
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return mchp_ecia_unset_callback_by_dev(dev, src);
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}
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/*
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* Create a build time flag to know if any aggregated GIRQ has been enabled.
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* We make use of DT FOREACH macro to check GIRQ node status.
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* Enabling a GIRQ node (status = "okay") implies you want it used in
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* aggregated mode. Note, GIRQ 8-12, 24-26 are aggregated only by HW design.
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* If a GIRQ node is disabled(status = "disabled") and is direct capable the
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* other driver/application may use IRQ_CONNECT, irq_enable, and the helper
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* functions in this driver to set/clear GIRQ enable bits and status.
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* Leaving a node disabled also allows another driver/application to take over
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* aggregation by managing the GIRQ itself.
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*/
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#define XEC_CHK_REQ_AGGR(n) DT_NODE_HAS_STATUS(n, okay) |
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#define XEC_ECIA_REQUIRE_AGGR_ISR \
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( \
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DT_FOREACH_CHILD(DT_NODELABEL(ecia), XEC_CHK_REQ_AGGR) \
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0)
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/* static const uint32_t xec_chk_req = (XEC_ECIA_REQUIRE_AGGR_ISR); */
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#if XEC_ECIA_REQUIRE_AGGR_ISR
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/*
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* Generic ISR for aggregated GIRQ's.
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* GIRQ source(status) bits are latched (R/W1C). The peripheral status
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* connected to the GIRQ source bit must be cleared first by the callback
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* and this routine will clear the GIRQ source bit. If a callback was not
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* registered for a source the enable will also be cleared to prevent
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* interrupt storms.
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* NOTE: dev_girq is a pointer to a GIRQ child device instance.
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*/
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static void xec_girq_isr(const struct device *dev_girq)
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{
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const struct xec_girq_config *const cfg = DEV_GIRQ_CFG(dev_girq);
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struct xec_girq_src_data *data = DEV_GIRQ_DATA(dev_girq);
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struct girq_regs *girq = (struct girq_regs *)cfg->base;
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int girq_id = GIRQ_ID_TO_BITPOS(cfg->girq_id);
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uint32_t idx = 0;
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uint32_t result = girq->RESULT;
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for (int i = 0; result && i < 32; i++) {
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uint8_t bitpos = 31 - (__builtin_clz(result) & 0x1f);
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/* is it an implemented source? */
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if (cfg->sources[bitpos] & BIT(7)) {
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/* yes, get the index by removing bit[7] flag */
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idx = (uint32_t)cfg->sources[bitpos] & ~BIT(7);
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/* callback registered? */
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if (data[idx].cb) {
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data[idx].cb(girq_id, bitpos, data[idx].data);
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} else { /* no callback, clear the enable */
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girq->EN_CLR = BIT(bitpos);
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}
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} else { /* paranoia, we should not get here... */
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girq->EN_CLR = BIT(bitpos);
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}
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/* clear GIRQ latched status */
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girq->SRC = BIT(bitpos);
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result &= ~BIT(bitpos);
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}
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}
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#endif
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/**
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* @brief initialize XEC ECIA driver
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* NOTE: GIRQ22 is special used for waking the PLL from deep sleep when a
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* peripheral receives data from an external entity (eSPI, I2C, etc). Once
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* the data transfer is complete the system re-enters deep sleep unless the
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* peripheral was configured to wake CPU after reception of data or event.
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* GIRQ22 aggregated output and sources are not connected to the NVIC.
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* We enable GIRQ22 aggregated output to ensure clock asynchronous wake
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* functionality is operational.
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*/
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static int xec_ecia_init(const struct device *dev)
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{
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const struct xec_ecia_config *cfg =
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(const struct xec_ecia_config *const) (dev->config);
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const struct device *const clk_dev = DEVICE_DT_GET(DT_NODELABEL(pcr));
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struct ecs_regs *const ecs = ECS_XEC_REG_BASE;
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struct ecia_regs *const ecia = (struct ecia_regs *)cfg->ecia_base;
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uint32_t n = 0, nr = 0;
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int ret;
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ret = clock_control_on(clk_dev,
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(clock_control_subsys_t *)&cfg->clk_ctrl);
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if (ret < 0) {
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return ret;
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}
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/* Enable all direct NVIC connections */
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ecs->INTR_CTRL |= BIT(0);
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/* gate off all aggregated outputs */
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ecia->BLK_EN_CLR = UINT32_MAX;
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/* connect aggregated only GIRQs to NVIC */
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ecia->BLK_EN_SET = MCHP_ECIA_AGGR_BITMAP;
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/* Clear all GIRQn source enables */
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for (n = 0; n < MCHP_GIRQS; n++) {
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ecia->GIRQ[n].EN_CLR = UINT32_MAX;
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}
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/* Clear all external NVIC enables and pending status */
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nr = SCnSCB->ICTR;
|
||||
for (n = 0u; n <= nr; n++) {
|
||||
NVIC->ICER[n] = UINT32_MAX;
|
||||
NVIC->ICPR[n] = UINT32_MAX;
|
||||
}
|
||||
|
||||
/* ecia->BLK_ACTIVE = xec_chk_req; */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* xec_config_girq_xxx.sources[] entries from GIRQ node */
|
||||
#define XEC_GIRQ_SOURCES2(node_id, prop, idx) \
|
||||
.sources[DT_PROP_BY_IDX(node_id, prop, idx)] = \
|
||||
((uint8_t)(idx) | BIT(7)),
|
||||
|
||||
/* Parameter n is a child node-id */
|
||||
#define GIRQ_XEC_DEVICE(n) \
|
||||
static int xec_girq_init_##n(const struct device *dev); \
|
||||
\
|
||||
static struct xec_girq_src_data \
|
||||
xec_data_girq_##n[DT_PROP_LEN(n, sources)]; \
|
||||
\
|
||||
static const struct xec_girq_config xec_config_girq_##n = { \
|
||||
.base = DT_REG_ADDR(n), \
|
||||
.girq_id = DT_PROP(n, girq_id), \
|
||||
.num_srcs = DT_PROP_LEN(n, sources), \
|
||||
DT_FOREACH_PROP_ELEM(n, sources, XEC_GIRQ_SOURCES2) \
|
||||
}; \
|
||||
\
|
||||
DEVICE_DT_DEFINE(n, xec_girq_init_##n, \
|
||||
NULL, &xec_data_girq_##n, &xec_config_girq_##n, \
|
||||
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
|
||||
NULL); \
|
||||
\
|
||||
static int xec_girq_init_##n(const struct device *dev) \
|
||||
{ \
|
||||
mchp_xec_ecia_girq_aggr_en( \
|
||||
GIRQ_ID_TO_BITPOS(DT_PROP(n, girq_id)), 1); \
|
||||
\
|
||||
IRQ_CONNECT(DT_IRQN(n), \
|
||||
DT_IRQ(n, priority), \
|
||||
xec_girq_isr, \
|
||||
DEVICE_DT_GET(n), 0); \
|
||||
\
|
||||
irq_enable(DT_IRQN(n)); \
|
||||
\
|
||||
return 0; \
|
||||
}
|
||||
|
||||
/*
|
||||
* iterate over each enabled child node of ECIA
|
||||
* Enable means property status = "okay"
|
||||
*/
|
||||
DT_FOREACH_CHILD_STATUS_OKAY(DT_NODELABEL(ecia), GIRQ_XEC_DEVICE)
|
||||
|
||||
/* n = GIRQ node id */
|
||||
#define XEC_GIRQ_HANDLE(n) \
|
||||
.girq_node_handles[DT_PROP(n, girq_id)] = (DEVICE_DT_GET(n)),
|
||||
|
||||
static const struct xec_ecia_config xec_config_ecia = {
|
||||
.ecia_base = DT_REG_ADDR(DT_NODELABEL(ecia)),
|
||||
.clk_ctrl = {
|
||||
.pcr_info = ECIA_XEC_PCR_INFO,
|
||||
},
|
||||
DT_FOREACH_CHILD_STATUS_OKAY(DT_NODELABEL(ecia), XEC_GIRQ_HANDLE)
|
||||
};
|
||||
|
||||
DEVICE_DT_DEFINE(DT_NODELABEL(ecia), xec_ecia_init,
|
||||
NULL, NULL, &xec_config_ecia,
|
||||
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
||||
NULL);
|
||||
|
||||
/* look up GIRQ node handle from ECIA configuration */
|
||||
static const struct device *get_girq_dev(int girq_num)
|
||||
{
|
||||
if ((girq_num < MCHP_FIRST_GIRQ) || (girq_num > MCHP_LAST_GIRQ)) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* safe to convert to zero based index */
|
||||
girq_num -= MCHP_FIRST_GIRQ;
|
||||
|
||||
return xec_config_ecia.girq_node_handles[girq_num];
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue