drivers: i2s: i2s_sam_ssc: Convert to devicetree

Convert i2s_sam_ssc driver to utilize devicetree.  We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree.  We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

boards/arm/sam_e70_xplained/Kconfig.defconfig

@@ -8,16 +8,6 @@ if BOARD_SAM_E70_XPLAINED
 config BOARD
 	default "sam_e70_xplained"
 
-if I2S
-
-config I2S_SAM_SSC_0_DMA_RX_CHANNEL
-	default 22
-
-config I2S_SAM_SSC_0_DMA_TX_CHANNEL
-	default 23
-
-endif # I2S
-
 if ETH_SAM_GMAC
 
 # Read MAC address from AT24MAC402 EEPROM

boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi

@@ -126,3 +126,12 @@
 		};
 	};
 };
+
+&ssc {
+	status = "okay";
+	label = "I2S_0";
+	dma-names = "rx", "tx";
+	dmas = <&xdmac 22 DMA_PERID_SSC_RX>, <&xdmac 23 DMA_PERID_SSC_TX>;
+	pinctrl-0 = <&pd24b_ssc_rf &pa22a_ssc_rk &pa10c_ssc_rd
+		     &pb0d_ssc_tf &pb1d_ssc_tk &pb5d_ssc_td>;
+};

boards/arm/sam_v71_xult/Kconfig.defconfig

@@ -9,15 +9,6 @@ if BOARD_SAM_V71_XULT
 config BOARD
 	default "sam_v71_xult"
 
-if I2S
-
-config I2S_SAM_SSC_0_DMA_RX_CHANNEL
-	default 22
-
-config I2S_SAM_SSC_0_DMA_TX_CHANNEL
-	default 23
-endif # I2S
-
 if ETH_SAM_GMAC
 
 # Read MAC address from AT24MAC402 EEPROM

boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi

@@ -156,3 +156,12 @@
 		};
 	};
 };
+
+&ssc {
+	status = "okay";
+	label = "I2S_0";
+	dma-names = "rx", "tx";
+	dmas = <&xdmac 22 DMA_PERID_SSC_RX>, <&xdmac 23 DMA_PERID_SSC_TX>;
+	pinctrl-0 = <&pd24b_ssc_rf &pa22a_ssc_rk &pa10c_ssc_rd
+		     &pb0d_ssc_tf &pb1d_ssc_tk &pb5d_ssc_td>;
+};

drivers/i2s/Kconfig.sam_ssc

@@ -21,46 +21,6 @@ config I2S_SAM_SSC_TX_BLOCK_COUNT
 	int "TX queue length"
 	default 4
 
-config I2S_SAM_SSC_0_NAME
-	string "I2S 0 device name"
-	default "I2S_0"
-
-config I2S_SAM_SSC_0_IRQ_PRI
-	int "Interrupt priority"
-	default 0
-
-config I2S_SAM_SSC_DMA_NAME
-	string "DMA device name"
-	default "DMA_0"
-	help
-	  Name of the DMA device this device driver can use.
-
-config I2S_SAM_SSC_0_DMA_RX_CHANNEL
-	int "DMA RX channel"
-	help
-	  DMA channel number to use for RX transfers.
-
-config I2S_SAM_SSC_0_DMA_TX_CHANNEL
-	int "DMA TX channel"
-	help
-	  DMA channel number to use for TX transfers.
-
-choice I2S_SAM_SSC_0_PIN_TD_SELECT
-	prompt "TD pin"
-	depends on SOC_SERIES_SAME70 || \
-		   SOC_SERIES_SAMV71
-
-	config I2S_SAM_SSC_0_PIN_TD_PB5
-		bool "PB5"
-
-	config I2S_SAM_SSC_0_PIN_TD_PD10
-		bool "PD10"
-
-	config I2S_SAM_SSC_0_PIN_TD_PD26
-		bool "PD26"
-
-endchoice # I2S_SAM_SSC_0_PIN_TD_SELECT
-
 config I2S_SAM_SSC_0_PIN_RF_EN
 	bool "RF pin enabled"
 	default y

drivers/i2s/i2s_sam_ssc.c

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#define DT_DRV_COMPAT atmel_sam_ssc
+
 /** @file
  * @brief I2S bus (SSC) driver for Atmel SAM MCU family.
  *
@@ -920,9 +922,9 @@ static int i2s_sam_initialize(struct device *dev)
 	k_sem_init(&dev_data->tx.sem, CONFIG_I2S_SAM_SSC_TX_BLOCK_COUNT,
 		   CONFIG_I2S_SAM_SSC_TX_BLOCK_COUNT);
 
-	dev_data->dev_dma = device_get_binding(CONFIG_I2S_SAM_SSC_DMA_NAME);
+	dev_data->dev_dma = device_get_binding(DT_INST_DMAS_LABEL_BY_NAME(0, tx));
 	if (!dev_data->dev_dma) {
-		LOG_ERR("%s device not found", CONFIG_I2S_SAM_SSC_DMA_NAME);
+		LOG_ERR("%s device not found", DT_INST_DMAS_LABEL_BY_NAME(0, tx));
 		return -ENODEV;
 	}
 
@@ -962,28 +964,17 @@ static struct device *get_dev_from_dma_channel(u32_t dma_channel)
 
 static void i2s0_sam_irq_config(void)
 {
-	IRQ_CONNECT(SSC_IRQn, CONFIG_I2S_SAM_SSC_0_IRQ_PRI, i2s_sam_isr,
+	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), i2s_sam_isr,
 		    DEVICE_GET(i2s0_sam), 0);
 }
 
-static const struct soc_gpio_pin i2s0_pins[] = {
+static const struct soc_gpio_pin i2s0_pins[] = ATMEL_SAM_DT_PINS(0);
-	PIN_SSC0_TK,
-	PIN_SSC0_TF,
-	PIN_SSC0_TD,
-#ifdef CONFIG_I2S_SAM_SSC_0_PIN_RK_EN
-	PIN_SSC0_RK,
-#endif
-#ifdef CONFIG_I2S_SAM_SSC_0_PIN_RF_EN
-	PIN_SSC0_RF,
-#endif
-	PIN_SSC0_RD,
-};
 
 static const struct i2s_sam_dev_cfg i2s0_sam_config = {
-	.regs = SSC,
+	.regs = (Ssc *)DT_INST_REG_ADDR(0),
 	.irq_config = i2s0_sam_irq_config,
-	.periph_id = ID_SSC,
+	.periph_id = DT_INST_PROP(0, peripheral_id),
-	.irq_id = SSC_IRQn,
+	.irq_id = DT_INST_IRQN(0),
 	.pin_list = i2s0_pins,
 	.pin_list_size = ARRAY_SIZE(i2s0_pins),
 };
@@ -993,10 +984,10 @@ struct queue_item tx_0_ring_buf[CONFIG_I2S_SAM_SSC_TX_BLOCK_COUNT + 1];
 
 static struct i2s_sam_dev_data i2s0_sam_data = {
 	.rx = {
-		.dma_channel = CONFIG_I2S_SAM_SSC_0_DMA_RX_CHANNEL,
+		.dma_channel = DT_INST_DMAS_CELL_BY_NAME(0, rx, channel),
 		.dma_cfg = {
 			.block_count = 1,
-			.dma_slot = DMA_PERID_SSC_RX,
+			.dma_slot = DT_INST_DMAS_CELL_BY_NAME(0, rx, perid),
 			.channel_direction = PERIPHERAL_TO_MEMORY,
 			.source_burst_length = 1,
 			.dest_burst_length = 1,
@@ -1010,10 +1001,10 @@ static struct i2s_sam_dev_data i2s0_sam_data = {
 		.set_data_format = set_rx_data_format,
 	},
 	.tx = {
-		.dma_channel = CONFIG_I2S_SAM_SSC_0_DMA_TX_CHANNEL,
+		.dma_channel = DT_INST_DMAS_CELL_BY_NAME(0, tx, channel),
 		.dma_cfg = {
 			.block_count = 1,
-			.dma_slot = DMA_PERID_SSC_TX,
+			.dma_slot = DT_INST_DMAS_CELL_BY_NAME(0, tx, perid),
 			.channel_direction = MEMORY_TO_PERIPHERAL,
 			.source_burst_length = 1,
 			.dest_burst_length = 1,
@@ -1028,6 +1019,6 @@ static struct i2s_sam_dev_data i2s0_sam_data = {
 	},
 };
 
-DEVICE_AND_API_INIT(i2s0_sam, CONFIG_I2S_SAM_SSC_0_NAME, &i2s_sam_initialize,
+DEVICE_AND_API_INIT(i2s0_sam, DT_INST_LABEL(0), &i2s_sam_initialize,
 		    &i2s0_sam_data, &i2s0_sam_config, POST_KERNEL,
 		    CONFIG_I2S_INIT_PRIORITY, &i2s_sam_driver_api);

dts/arm/atmel/sam3x-pinctrl.dtsi

@@ -20,6 +20,12 @@
 			DT_ATMEL_PIN(spi0, npcs3, a, 31, a);
 			DT_ATMEL_PIN(spi0, npcs3, b, 23, b);
 			DT_ATMEL_PIN(spi0, spck, a, 27, a);
+			DT_ATMEL_PIN(ssc, rd, b, 18, a);
+			DT_ATMEL_PIN(ssc, rf, b, 17, a);
+			DT_ATMEL_PIN(ssc, rk, b, 19, a);
+			DT_ATMEL_PIN(ssc, td, a, 16, b);
+			DT_ATMEL_PIN(ssc, tf, a, 15, b);
+			DT_ATMEL_PIN(ssc, tk, a, 14, b);
 			DT_ATMEL_PIN(twi0, twck0, a, 18, a);
 			DT_ATMEL_PIN(twi0, twd0, a, 17, a);
 			DT_ATMEL_PIN(twi1, twck1, b, 13, a);

dts/arm/atmel/sam4s-pinctrl.dtsi

@@ -24,6 +24,12 @@
 			DT_ATMEL_PIN(spi, npcs3, a, 5, b);
 			DT_ATMEL_PIN(spi, npcs3, a, 22, b);
 			DT_ATMEL_PIN(spi, spck, a, 14, a);
+			DT_ATMEL_PIN(ssc, rd, a, 18, a);
+			DT_ATMEL_PIN(ssc, rf, a, 20, a);
+			DT_ATMEL_PIN(ssc, rk, a, 19, a);
+			DT_ATMEL_PIN(ssc, td, a, 17, a);
+			DT_ATMEL_PIN(ssc, tf, a, 15, a);
+			DT_ATMEL_PIN(ssc, tk, a, 16, a);
 			DT_ATMEL_PIN(twi0, twck0, a, 4, a);
 			DT_ATMEL_PIN(twi0, twd0, a, 3, a);
 			DT_ATMEL_PIN(twi1, twck1, b, 5, a);

dts/arm/atmel/same70-pinctrl.dtsi

@@ -52,6 +52,14 @@
 			DT_ATMEL_PIN(spi1, npcs3, c, 30, c);
 			DT_ATMEL_PIN(spi1, npcs3, d, 2, c);
 			DT_ATMEL_PIN(spi1, spck, c, 24, c);
+			DT_ATMEL_PIN(ssc, rd, a, 10, c);
+			DT_ATMEL_PIN(ssc, rf, d, 24, b);
+			DT_ATMEL_PIN(ssc, rk, a, 22, a);
+			DT_ATMEL_PIN(ssc, td, b, 5, d);
+			DT_ATMEL_PIN(ssc, td, d, 10, c);
+			DT_ATMEL_PIN(ssc, td, d, 26, b);
+			DT_ATMEL_PIN(ssc, tf, b, 0, d);
+			DT_ATMEL_PIN(ssc, tk, b, 1, d);
 			DT_ATMEL_PIN(twihs0, twck0, a, 4, a);
 			DT_ATMEL_PIN(twihs0, twd0, a, 3, a);
 			DT_ATMEL_PIN(twihs1, twck1, b, 5, a);

dts/arm/atmel/same70.dtsi

@@ -372,6 +372,15 @@
 			label = "DMA_0";
 			#dma-cells = <2>;
 		};
+
+		ssc: ssc@40004000 {
+			compatible = "atmel,sam-ssc";
+			reg = <0x40004000 0x400>;
+			interrupts = <22 0>;
+			peripheral-id = <22>;
+			label = "SSC_0";
+			status = "disabled";
+		};
 	};
 };
 

dts/bindings/arm/atmel,sam-ssc.yaml

@@ -0,0 +1,52 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM SSC (Synchronous Serial Controller) controller
+
+compatible: "atmel,sam-ssc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      description: |
+        PIO pin configuration for RF, RK, RD, TF, TK, & TD signals.
+        We expect that the phandles will reference pinctrl nodes.
+        These nodes will have a nodelabel that matches the Atmel SoC HAL
+        defines and be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the SSC on SAME7x would be
+           pinctrl-0 = <&pd24b_ssc_rf &pa22a_ssc_rk &pa10c_ssc_rd
+                        &pb0d_ssc_tf &pb1d_ssc_tk &pb5d_ssc_td>;
+
+      required: true
+
+    dmas:
+      required: true
+      description: |
+        TX & RX dma specifiers.  Each specifier will have a phandle
+        reference to the dma controller, the channel number, and peripheral
+        trigger source.
+
+        For example dmas for TX, RX would look like
+           dmas = <&xdmac 22 DMA_PERID_SSC_TX>, <&xdmac 23 DMA_PERID_SSC_RX>;
+
+    dma-names:
+      required: true
+      description: |
+        This should be "tx" and "rx" to match the dmas property.
+
+        For example
+           dma-names = "tx", "rx";

soc/arm/atmel_sam/same70/soc.h

@@ -79,49 +79,4 @@
 
 #endif /* _ASMLANGUAGE */
 
-/** Peripheral Hardware Request Line Identifier */
-#define DMA_PERID_HSMCI_TX_RX 0
-#define DMA_PERID_SPI0_TX     1
-#define DMA_PERID_SPI0_RX     2
-#define DMA_PERID_SPI1_TX     3
-#define DMA_PERID_SPI1_RX     4
-#define DMA_PERID_QSPI_TX     5
-#define DMA_PERID_QSPI_RX     6
-#define DMA_PERID_USART0_TX   7
-#define DMA_PERID_USART0_RX   8
-#define DMA_PERID_USART1_TX   9
-#define DMA_PERID_USART1_RX   10
-#define DMA_PERID_USART2_TX   11
-#define DMA_PERID_USART2_RX   12
-#define DMA_PERID_PWM0_TX     13
-#define DMA_PERID_TWIHS0_TX   14
-#define DMA_PERID_TWIHS0_RX   15
-#define DMA_PERID_TWIHS1_TX   16
-#define DMA_PERID_TWIHS1_RX   17
-#define DMA_PERID_TWIHS2_TX   18
-#define DMA_PERID_TWIHS2_RX   19
-#define DMA_PERID_UART0_TX    20
-#define DMA_PERID_UART0_RX    21
-#define DMA_PERID_UART1_TX    22
-#define DMA_PERID_UART1_RX    23
-#define DMA_PERID_UART2_TX    24
-#define DMA_PERID_UART2_RX    25
-#define DMA_PERID_UART3_TX    26
-#define DMA_PERID_UART3_RX    27
-#define DMA_PERID_UART4_TX    28
-#define DMA_PERID_UART4_RX    29
-#define DMA_PERID_DACC_TX     30
-#define DMA_PERID_SSC_TX      32
-#define DMA_PERID_SSC_RX      33
-#define DMA_PERID_PIOA_RX     34
-#define DMA_PERID_AFEC0_RX    35
-#define DMA_PERID_AFEC1_RX    36
-#define DMA_PERID_AES_TX      37
-#define DMA_PERID_AES_RX      38
-#define DMA_PERID_PWM1_TX     39
-#define DMA_PERID_TC0_RX      40
-#define DMA_PERID_TC1_RX      41
-#define DMA_PERID_TC2_RX      42
-#define DMA_PERID_TC3_RX      43
-
 #endif /* _ATMEL_SAME70_SOC_H_ */

soc/arm/atmel_sam/samv71/soc.h

@@ -80,58 +80,4 @@
 
 #endif /* _ASMLANGUAGE */
 
-/** Peripheral Hardware Request Line Identifier */
-#define DMA_PERID_HSMCI_TX_RX 0
-#define DMA_PERID_SPI0_TX     1
-#define DMA_PERID_SPI0_RX     2
-#define DMA_PERID_SPI1_TX     3
-#define DMA_PERID_SPI1_RX     4
-#define DMA_PERID_QSPI_TX     5
-#define DMA_PERID_QSPI_RX     6
-#define DMA_PERID_USART0_TX   7
-#define DMA_PERID_USART0_RX   8
-#define DMA_PERID_USART1_TX   9
-#define DMA_PERID_USART1_RX   10
-#define DMA_PERID_USART2_TX   11
-#define DMA_PERID_USART2_RX   12
-#define DMA_PERID_PWM0_TX     13
-#define DMA_PERID_TWIHS0_TX   14
-#define DMA_PERID_TWIHS0_RX   15
-#define DMA_PERID_TWIHS1_TX   16
-#define DMA_PERID_TWIHS1_RX   17
-#define DMA_PERID_TWIHS2_TX   18
-#define DMA_PERID_TWIHS2_RX   19
-#define DMA_PERID_UART0_TX    20
-#define DMA_PERID_UART0_RX    21
-#define DMA_PERID_UART1_TX    22
-#define DMA_PERID_UART1_RX    23
-#define DMA_PERID_UART2_TX    24
-#define DMA_PERID_UART2_RX    25
-#define DMA_PERID_UART3_TX    26
-#define DMA_PERID_UART3_RX    27
-#define DMA_PERID_UART4_TX    28
-#define DMA_PERID_UART4_RX    29
-#define DMA_PERID_DACC0_TX    30
-#define DMA_PERID_DACC1_TX    31
-#define DMA_PERID_SSC_TX      32
-#define DMA_PERID_SSC_RX      33
-#define DMA_PERID_PIOA_RX     34
-#define DMA_PERID_AFEC0_RX    35
-#define DMA_PERID_AFEC1_RX    36
-#define DMA_PERID_AES_TX      37
-#define DMA_PERID_AES_RX      38
-#define DMA_PERID_PWM1_TX     39
-#define DMA_PERID_TC0_RX      40
-#define DMA_PERID_TC3_RX      41
-#define DMA_PERID_TC6_RX      42
-#define DMA_PERID_TC9_RX      43
-#define DMA_PERID_I2SC0_TX_L  44
-#define DMA_PERID_I2SC0_RX_L  45
-#define DMA_PERID_I2SC1_TX_L  46
-#define DMA_PERID_I2SC1_RX_L  47
-#define DMA_PERID_I2SC0_TX_R  48
-#define DMA_PERID_I2SC0_RX_R  49
-#define DMA_PERID_I2SC1_TX_R  50
-#define DMA_PERID_I2SC1_RX_R  51
-
 #endif /* _ATMEL_SAMV71_SOC_H_ */