xtensa: use inline assembly instead of XT_* macros
XT_* macros are defined in xtensa HAL headers as xcc intrinsics. gcc does not have any of these intrinsics. Replace XT_* macros with inline assembly or provide gcc-compatible definitions. Change-Id: If823ea8a7898a11a3a8363b17efdba27dee4c6a4 Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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2 changed files with 36 additions and 4 deletions
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@ -19,7 +19,7 @@ void k_cpu_idle(void)
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
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_sys_k_event_logger_enter_sleep();
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#endif
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XT_WAITI(0);
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__asm__ volatile ("waiti 0");
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}
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/*
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* @brief Put the CPU in low-power mode, entered with IRQs locked
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@ -33,7 +33,7 @@ void k_cpu_atomic_idle(unsigned int key)
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
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_sys_k_event_logger_enter_sleep();
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#endif
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XT_WAITI(0);
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XT_WSR_PS(key);
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XT_RSYNC();
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__asm__ volatile ("waiti 0\n\t"
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"wsr.ps %0\n\t"
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"rsync" :: "a"(key));
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}
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@ -39,6 +39,38 @@
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#define GET_TIMER_FIRE_TIME(void) XT_SR_CCOMPARE(R, XT_TIMER_INDEX)()
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#define SET_TIMER_FIRE_TIME(time) XT_SR_CCOMPARE(W, XT_TIMER_INDEX)(time)
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#define GET_TIMER_CURRENT_TIME(void) XT_RSR_CCOUNT()
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#define XTENSA_RSR(sr) \
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({uint32_t v; \
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__asm__ volatile ("rsr." #sr " %0" : "=a"(v)); \
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v; })
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#define XTENSA_WSR(sr, v) \
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({__asm__ volatile ("wsr." #sr " %0" :: "a"(v)); })
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#ifndef XT_RSR_CCOUNT
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#define XT_RSR_CCOUNT() XTENSA_RSR(ccount)
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#endif
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#ifndef XT_RSR_CCOMPARE0
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#define XT_RSR_CCOMPARE0() XTENSA_RSR(ccompare0)
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#endif
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#ifndef XT_RSR_CCOMPARE1
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#define XT_RSR_CCOMPARE1() XTENSA_RSR(ccompare1)
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#endif
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#ifndef XT_RSR_CCOMPARE2
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#define XT_RSR_CCOMPARE2() XTENSA_RSR(ccompare2)
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#endif
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#ifndef XT_WSR_CCOMPARE0
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#define XT_WSR_CCOMPARE0(v) XTENSA_WSR(ccompare0, v)
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#endif
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#ifndef XT_WSR_CCOMPARE1
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#define XT_WSR_CCOMPARE1(v) XTENSA_WSR(ccompare1, v)
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#endif
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#ifndef XT_WSR_CCOMPARE2
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#define XT_WSR_CCOMPARE2(v) XTENSA_WSR(ccompare2, v)
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#endif
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/* Value underwich, don't program next tick but trigger it immediately. */
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#define MIN_TIMER_PROG_DELAY 50
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#else /* Case of an external timer which is not emulated by internal timer */
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