michaelh/zephyr
1
0
Fork 0
Code Releases Activity

xtensa: use inline assembly instead of XT_* macros

Browse source 
XT_* macros are defined in xtensa HAL headers as xcc intrinsics. gcc
does not have any of these intrinsics. Replace XT_* macros with inline
assembly or provide gcc-compatible definitions.

Change-Id: If823ea8a7898a11a3a8363b17efdba27dee4c6a4
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2017-02-15 14:57:29 -08:00 • committed by Anas Nashif
commit 6a89999787
2 changed files with 36 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

8
arch/xtensa/core/cpu_idle.c
View file

@ -19,7 +19,7 @@ void k_cpu_idle(void)
#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
_sys_k_event_logger_enter_sleep(); _sys_k_event_logger_enter_sleep();
#endif #endif
XT_WAITI(0); __asm__ volatile ("waiti 0");
} }
/* /*
* @brief Put the CPU in low-power mode, entered with IRQs locked * @brief Put the CPU in low-power mode, entered with IRQs locked
@ -33,7 +33,7 @@ void k_cpu_atomic_idle(unsigned int key)
#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
_sys_k_event_logger_enter_sleep(); _sys_k_event_logger_enter_sleep();
#endif #endif
XT_WAITI(0); __asm__ volatile ("waiti 0\n\t"
XT_WSR_PS(key); "wsr.ps %0\n\t"
XT_RSYNC(); "rsync" :: "a"(key));
} }

32
drivers/timer/xtensa_sys_timer.c
View file

@ -39,6 +39,38 @@
#define GET_TIMER_FIRE_TIME(void) XT_SR_CCOMPARE(R, XT_TIMER_INDEX)() #define GET_TIMER_FIRE_TIME(void) XT_SR_CCOMPARE(R, XT_TIMER_INDEX)()
#define SET_TIMER_FIRE_TIME(time) XT_SR_CCOMPARE(W, XT_TIMER_INDEX)(time) #define SET_TIMER_FIRE_TIME(time) XT_SR_CCOMPARE(W, XT_TIMER_INDEX)(time)
#define GET_TIMER_CURRENT_TIME(void) XT_RSR_CCOUNT() #define GET_TIMER_CURRENT_TIME(void) XT_RSR_CCOUNT()
#define XTENSA_RSR(sr) \
({uint32_t v; \
__asm__ volatile ("rsr." #sr " %0" : "=a"(v)); \
v; })
#define XTENSA_WSR(sr, v) \
({__asm__ volatile ("wsr." #sr " %0" :: "a"(v)); })
#ifndef XT_RSR_CCOUNT
#define XT_RSR_CCOUNT() XTENSA_RSR(ccount)
#endif
#ifndef XT_RSR_CCOMPARE0
#define XT_RSR_CCOMPARE0() XTENSA_RSR(ccompare0)
#endif
#ifndef XT_RSR_CCOMPARE1
#define XT_RSR_CCOMPARE1() XTENSA_RSR(ccompare1)
#endif
#ifndef XT_RSR_CCOMPARE2
#define XT_RSR_CCOMPARE2() XTENSA_RSR(ccompare2)
#endif
#ifndef XT_WSR_CCOMPARE0
#define XT_WSR_CCOMPARE0(v) XTENSA_WSR(ccompare0, v)
#endif
#ifndef XT_WSR_CCOMPARE1
#define XT_WSR_CCOMPARE1(v) XTENSA_WSR(ccompare1, v)
#endif
#ifndef XT_WSR_CCOMPARE2
#define XT_WSR_CCOMPARE2(v) XTENSA_WSR(ccompare2, v)
#endif
/* Value underwich, don't program next tick but trigger it immediately. */ /* Value underwich, don't program next tick but trigger it immediately. */
#define MIN_TIMER_PROG_DELAY 50 #define MIN_TIMER_PROG_DELAY 50
#else /* Case of an external timer which is not emulated by internal timer */ #else /* Case of an external timer which is not emulated by internal timer */