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drivers: adc: stm32: ADC nocache buffers can be in CONFIG_NOCACHE_MEMORY

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CONFIG_NOCACHE_MEMORY is a valid way of declaring buffers in
nocache regions. Consider them valid in the STM32 ADC driver
nocache check.
Copied from commit 818aa2d

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier 2023-09-20 15:41:09 +02:00 • committed by Johan Hedberg
commit 69fb18a19d
1 changed files with 22 additions and 4 deletions
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26
drivers/adc/adc_stm32.c
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@ -43,7 +43,16 @@ LOG_MODULE_REGISTER(adc_stm32);
#include <zephyr/dt-bindings/adc/stm32_adc.h> #include <zephyr/dt-bindings/adc/stm32_adc.h>
#include <zephyr/irq.h> #include <zephyr/irq.h>
#include <zephyr/mem_mgmt/mem_attr.h> #include <zephyr/mem_mgmt/mem_attr.h>
#ifdef CONFIG_SOC_SERIES_STM32H7X
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
#endif
#ifdef CONFIG_NOCACHE_MEMORY
#include <zephyr/linker/linker-defs.h>
#elif defined(CONFIG_CACHE_MANAGEMENT)
#include <zephyr/arch/cache.h>
#endif /* CONFIG_NOCACHE_MEMORY */
#if defined(CONFIG_SOC_SERIES_STM32F3X) #if defined(CONFIG_SOC_SERIES_STM32F3X)
#if defined(ADC1_V2_5) #if defined(ADC1_V2_5)
@ -285,13 +294,22 @@ static int adc_stm32_dma_start(const struct device *dev,
* zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) | ... )>; * zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) | ... )>;
* }; * };
*/ */
static bool address_in_non_cacheable_sram(const uint16_t *buffer, const uint16_t size) static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
{ {
if (mem_attr_check_buf((void *) buffer, (size_t) size, DT_MEM_ARM_MPU_RAM_NOCACHE) == 0) { bool buf_within_nocache = false;
#ifdef CONFIG_NOCACHE_MEMORY
buf_within_nocache = (buf >= ((uintptr_t)_nocache_ram_start)) &&
((buf + len_bytes - 1) <= ((uintptr_t)_nocache_ram_end));
if (buf_within_nocache) {
return true; return true;
} }
#endif /* CONFIG_NOCACHE_MEMORY */
return false; buf_within_nocache = mem_attr_check_buf(
(void *)buf, len_bytes, DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)) == 0;
return buf_within_nocache;
} }
#endif /* defined(CONFIG_ADC_STM32_DMA) && defined(CONFIG_SOC_SERIES_STM32H7X) */ #endif /* defined(CONFIG_ADC_STM32_DMA) && defined(CONFIG_SOC_SERIES_STM32H7X) */
@ -314,7 +332,7 @@ static int check_buffer(const struct adc_sequence *sequence,
#if defined(CONFIG_ADC_STM32_DMA) && defined(CONFIG_SOC_SERIES_STM32H7X) #if defined(CONFIG_ADC_STM32_DMA) && defined(CONFIG_SOC_SERIES_STM32H7X)
/* Buffer is forced to be in non-cacheable SRAM region to avoid cache maintenance */ /* Buffer is forced to be in non-cacheable SRAM region to avoid cache maintenance */
if (!address_in_non_cacheable_sram(sequence->buffer, needed_buffer_size)) { if (!buf_in_nocache((uintptr_t)sequence->buffer, needed_buffer_size)) {
LOG_ERR("Supplied buffer is not in a non-cacheable region according to DTS."); LOG_ERR("Supplied buffer is not in a non-cacheable region according to DTS.");
return -EINVAL; return -EINVAL;
} }