From 69d153cd3d72fd0f50ab662e83ea3af98bfc0049 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 25 May 2022 11:30:36 -0500 Subject: [PATCH] soc: nxp_imx: rt: enable SWO output for iMX RT 10xx series enable swo output for iMX RT 10xx series. SWO pinmux settings are currently only present for the RT1060 and RT1064 Signed-off-by: Daniel DeGrasse --- boards/arm/mimxrt1060_evk/doc/index.rst | 6 ++++++ .../arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi | 13 ++++++++++++- boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts | 5 +++++ boards/arm/mimxrt1064_evk/doc/index.rst | 6 ++++++ .../arm/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi | 12 +++++++++++- boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts | 5 +++++ dts/arm/nxp/nxp_rt.dtsi | 6 ++++++ soc/arm/nxp_imx/rt/Kconfig.defconfig.series | 4 ++++ soc/arm/nxp_imx/rt/Kconfig.soc | 13 +++++++++++++ soc/arm/nxp_imx/rt/soc_rt10xx.c | 9 +++++++++ 10 files changed, 77 insertions(+), 2 deletions(-) diff --git a/boards/arm/mimxrt1060_evk/doc/index.rst b/boards/arm/mimxrt1060_evk/doc/index.rst index 3ab337f96ad..4681219d1b4 100644 --- a/boards/arm/mimxrt1060_evk/doc/index.rst +++ b/boards/arm/mimxrt1060_evk/doc/index.rst @@ -333,6 +333,12 @@ etc.): - Parity: None - Stop bits: 1 +Using SWO +--------- +SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. +Your SWO viewer should be configured with a CPU frequency of 132MHz, and +SWO frequency of 7500KHz. + Flashing ======== diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi b/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi index aa64c222d33..7f70fbe5cea 100644 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi +++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi @@ -2,7 +2,7 @@ * Copyright (c) 2022, NXP * SPDX-License-Identifier: Apache-2.0 * - * Note: File generated by rt_cfg_utils.py + * Note: File generated by imx_cfg_utils.py * from mimxrt1060_evk.mex */ @@ -327,6 +327,17 @@ }; }; + /* Note SWO is configured with a cpu frequency of 132MHz and SWO frequency of 7500KHz */ + pinmux_swo: pinmux_swo { + group0 { + pinmux = <&iomuxc_gpio_ad_b0_10_arm_trace_swo>; + bias-disable; + drive-strength = "r0-7"; + slew-rate = "fast"; + nxp,speed = "200-mhz"; + }; + }; + pinmux_usdhc1: pinmux_usdhc1 { group0 { pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>; diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts index c43eb4056de..e3262839bf2 100644 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts +++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts @@ -286,3 +286,8 @@ zephyr_udc0: &usb1 { &iomuxcgpr { status = "okay"; }; + +&itm { + pinctrl-0 = <&pinmux_swo>; + pinctrl-names = "default"; +}; diff --git a/boards/arm/mimxrt1064_evk/doc/index.rst b/boards/arm/mimxrt1064_evk/doc/index.rst index d5dd1f1911d..0929a4c83b2 100644 --- a/boards/arm/mimxrt1064_evk/doc/index.rst +++ b/boards/arm/mimxrt1064_evk/doc/index.rst @@ -339,6 +339,12 @@ etc.): - Parity: None - Stop bits: 1 +Using SWO +--------- +SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. +Your SWO viewer should be configured with a CPU frequency of 132MHz, and +SWO frequency of 7500KHz. + Flashing ======== diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi b/boards/arm/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi index e6e7cf514fc..ca469201209 100644 --- a/boards/arm/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi +++ b/boards/arm/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi @@ -2,7 +2,7 @@ * Copyright (c) 2022, NXP * SPDX-License-Identifier: Apache-2.0 * - * Note: File generated by rt_cfg_utils.py + * Note: File generated by imx_cfg_utils.py * from mimxrt1064_evk.mex */ @@ -314,6 +314,16 @@ }; }; + /* note swo is configured with a cpu frequency of 132mhz and swo frequency of 7500khz */ + pinmux_swo: pinmux_swo { + group0 { + pinmux = <&iomuxc_gpio_ad_b0_10_arm_trace_swo>; + drive-strength = "r0-6"; + slew-rate = "fast"; + nxp,speed = "100-mhz"; + }; + }; + pinmux_usdhc1: pinmux_usdhc1 { group0 { pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>; diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts index 6eb5a0bc0b3..6c2851dacd6 100644 --- a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts +++ b/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts @@ -348,3 +348,8 @@ zephyr_udc0: &usb1 { &gpt_hw_timer { status = "okay"; }; + +&itm { + pinctrl-0 = <&pinmux_swo>; + pinctrl-names = "default"; +}; diff --git a/dts/arm/nxp/nxp_rt.dtsi b/dts/arm/nxp/nxp_rt.dtsi index 92c9928c9f7..55b1be2409e 100644 --- a/dts/arm/nxp/nxp_rt.dtsi +++ b/dts/arm/nxp/nxp_rt.dtsi @@ -33,6 +33,12 @@ reg = <0xe000ed90 0x40>; arm,num-mpu-regions = <16>; }; + + itm: itm@e0000000 { + compatible = "arm,armv7m-itm"; + reg = <0xe0000000 0x1000>; + swo-ref-frequency = <132000000>; + }; }; }; diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt/Kconfig.defconfig.series index 71c298c293b..dc3a6ccf880 100644 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series +++ b/soc/arm/nxp_imx/rt/Kconfig.defconfig.series @@ -64,6 +64,10 @@ config IMX_USDHC default y if (HAS_MCUX_USDHC1 || HAS_MCUX_USDHC2) depends on SDHC +config LOG_BACKEND_SWO_FREQ_HZ + default 7500000 + depends on LOG_BACKEND_SWO + if FLASH_MCUX_FLEXSPI_XIP # Avoid RWW hazards by defaulting logging to disabled diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc index a3a6b887983..4b2505cb5b3 100644 --- a/soc/arm/nxp_imx/rt/Kconfig.soc +++ b/soc/arm/nxp_imx/rt/Kconfig.soc @@ -29,6 +29,7 @@ config SOC_MIMXRT1011 select HAS_MCUX_DCDC select HAS_MCUX_PMU select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1015 bool "SOC_MIMXRT1015" @@ -53,6 +54,7 @@ config SOC_MIMXRT1015 select HAS_MCUX_DCDC select HAS_MCUX_PMU select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1021 bool "SOC_MIMXRT1021" @@ -83,6 +85,7 @@ config SOC_MIMXRT1021 select HAS_MCUX_DCDC select HAS_MCUX_PMU select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1024 bool "SOC_MIMXRT1024" @@ -113,6 +116,7 @@ config SOC_MIMXRT1024 select HAS_MCUX_DCDC select HAS_MCUX_PMU select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1051 bool "SOC_MIMXRT1051" @@ -143,6 +147,7 @@ config SOC_MIMXRT1051 select HAS_MCUX_DCDC select HAS_MCUX_PMU select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1052 bool "SOC_MIMXRT1052" @@ -177,6 +182,7 @@ config SOC_MIMXRT1052 select HAS_MCUX_DCDC select HAS_MCUX_PMU select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1061 bool "SOC_MIMXRT1061" @@ -207,6 +213,7 @@ config SOC_MIMXRT1061 select HAS_MCUX_DCDC select HAS_MCUX_PMU select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1062 bool "SOC_MIMXRT1062" @@ -246,6 +253,7 @@ config SOC_MIMXRT1062 select HAS_MCUX_IOMUXC select HAS_MCUX_ADC_ETC select HAS_MCUX_SRC + select HAS_SWO config SOC_MIMXRT1064 bool "SOC_MIMXRT1064" @@ -283,6 +291,7 @@ config SOC_MIMXRT1064 select HAS_MCUX_DCDC select HAS_MCUX_PMU select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1176_CM7 bool "SOC_MIMXRT1176_CM7" @@ -323,6 +332,7 @@ config SOC_MIMXRT1176_CM7 select HAS_MCUX_ACMP select HAS_MCUX_SRC_V2 select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1176_CM4 bool "SOC_MIMXRT1176_CM4" @@ -352,6 +362,7 @@ config SOC_MIMXRT1176_CM4 select HAS_MCUX_ACMP select HAS_MCUX_SRC_V2 select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1166_CM7 bool "SOC_MIMXRT1166_CM7" @@ -388,6 +399,7 @@ config SOC_MIMXRT1166_CM7 select HAS_MCUX_USB_EHCI select HAS_MCUX_SRC_V2 select HAS_MCUX_IOMUXC + select HAS_SWO config SOC_MIMXRT1166_CM4 @@ -416,6 +428,7 @@ config SOC_MIMXRT1166_CM4 select HAS_MCUX_GPC select HAS_MCUX_SRC_V2 select HAS_MCUX_IOMUXC + select HAS_SWO endchoice diff --git a/soc/arm/nxp_imx/rt/soc_rt10xx.c b/soc/arm/nxp_imx/rt/soc_rt10xx.c index 6f94f39a381..4c6de7845dd 100644 --- a/soc/arm/nxp_imx/rt/soc_rt10xx.c +++ b/soc/arm/nxp_imx/rt/soc_rt10xx.c @@ -212,6 +212,15 @@ static ALWAYS_INLINE void clock_init(void) CLOCK_SetMux(kCLOCK_CanMux, 2); /* Set Can clock source. */ #endif +#ifdef CONFIG_LOG_BACKEND_SWO + /* Enable ARM trace clock to enable SWO output */ + CLOCK_EnableClock(kCLOCK_Trace); + /* Divide root clock output by 3 */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Source clock from 528MHz system PLL */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); +#endif + /* Keep the system clock running so SYSTICK can wake up the system from * wfi. */