diff --git a/drivers/spi/spi_dw.c b/drivers/spi/spi_dw.c index 2f6ac844681..c760a9e8a2c 100644 --- a/drivers/spi/spi_dw.c +++ b/drivers/spi/spi_dw.c @@ -543,9 +543,17 @@ struct spi_dw_data spi_dw_data_port_0 = { SPI_CONTEXT_INIT_SYNC(spi_dw_data_port_0, ctx), }; +#ifdef DT_INST_0_SNPS_DESIGNWARE_SPI_CLOCKS_CLOCK_FREQUENCY +#define INST_0_SNPS_DESIGNWARE_SPI_CLOCK_FREQ \ + DT_INST_0_SNPS_DESIGNWARE_SPI_CLOCKS_CLOCK_FREQUENCY +#else +#define INST_0_SNPS_DESIGNWARE_SPI_CLOCK_FREQ \ + DT_INST_0_SNPS_DESIGNWARE_SPI_CLOCK_FREQUENCY +#endif + const struct spi_dw_config spi_dw_config_0 = { - .regs = DT_SPI_DW_0_BASE_ADDRESS, - .clock_frequency = DT_SPI_DW_0_CLOCK_FREQUENCY, + .regs = DT_INST_0_SNPS_DESIGNWARE_SPI_BASE_ADDRESS, + .clock_frequency = INST_0_SNPS_DESIGNWARE_SPI_CLOCK_FREQ, #ifdef CONFIG_SPI_DW_PORT_0_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS), @@ -554,32 +562,36 @@ const struct spi_dw_config spi_dw_config_0 = { .op_modes = CONFIG_SPI_0_OP_MODES }; -DEVICE_AND_API_INIT(spi_dw_port_0, DT_SPI_DW_0_NAME, spi_dw_init, - &spi_dw_data_port_0, &spi_dw_config_0, +DEVICE_AND_API_INIT(spi_dw_port_0, DT_INST_0_SNPS_DESIGNWARE_SPI_LABEL, + spi_dw_init, &spi_dw_data_port_0, &spi_dw_config_0, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &dw_spi_api); void spi_config_0_irq(void) { #ifdef CONFIG_SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(DT_SPI_DW_0_IRQ, DT_SPI_DW_0_IRQ_PRI, + IRQ_CONNECT(DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_0, + DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_0_PRIORITY, spi_dw_isr, DEVICE_GET(spi_dw_port_0), - DT_SPI_DW_0_IRQ_FLAGS); - irq_enable(DT_SPI_DW_0_IRQ); + DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_FLAGS); + irq_enable(DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_0); #else - IRQ_CONNECT(DT_SPI_DW_0_IRQ_RX_AVAIL, DT_SPI_DW_0_IRQ_RX_AVAIL_PRI, + IRQ_CONNECT(DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL, + DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), - DT_SPI_DW_0_IRQ_RX_AVAIL_FLAGS); - IRQ_CONNECT(DT_SPI_DW_0_IRQ_TX_REQ, DT_SPI_DW_0_IRQ_TX_REQ_PRI, + DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL_FLAGS); + IRQ_CONNECT(DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ, + DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), - DT_SPI_DW_0_IRQ_TX_REQ_FLAGS); - IRQ_CONNECT(DT_SPI_DW_0_IRQ_ERR_INT, DT_SPI_DW_0_IRQ_ERR_INT_PRI, + DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ_FLAGS); + IRQ_CONNECT(DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT, + DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), - DT_SPI_DW_0_IRQ_ERR_INT_FLAGS); + DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT_FLAGS); - irq_enable(DT_SPI_DW_0_IRQ_RX_AVAIL); - irq_enable(DT_SPI_DW_0_IRQ_TX_REQ); - irq_enable(DT_SPI_DW_0_IRQ_ERR_INT); + irq_enable(DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL); + irq_enable(DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ); + irq_enable(DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT); #endif } @@ -592,9 +604,17 @@ struct spi_dw_data spi_dw_data_port_1 = { SPI_CONTEXT_INIT_SYNC(spi_dw_data_port_1, ctx), }; +#ifdef DT_INST_1_SNPS_DESIGNWARE_SPI_CLOCKS_CLOCK_FREQUENCY +#define INST_1_SNPS_DESIGNWARE_SPI_CLOCK_FREQ \ + DT_INST_1_SNPS_DESIGNWARE_SPI_CLOCKS_CLOCK_FREQUENCY +#else +#define INST_1_SNPS_DESIGNWARE_SPI_CLOCK_FREQ \ + DT_INST_1_SNPS_DESIGNWARE_SPI_CLOCK_FREQUENCY +#endif + static const struct spi_dw_config spi_dw_config_1 = { - .regs = DT_SPI_DW_1_BASE_ADDRESS, - .clock_frequency = DT_SPI_DW_1_CLOCK_FREQUENCY, + .regs = DT_INST_1_SNPS_DESIGNWARE_SPI_BASE_ADDRESS, + .clock_frequency = INST_1_SNPS_DESIGNWARE_SPI_CLOCK_FREQ, #ifdef CONFIG_SPI_DW_PORT_1_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_1_CLOCK_GATE_SUBSYS), @@ -603,32 +623,36 @@ static const struct spi_dw_config spi_dw_config_1 = { .op_modes = CONFIG_SPI_1_OP_MODES }; -DEVICE_AND_API_INIT(spi_dw_port_1, DT_SPI_DW_1_NAME, spi_dw_init, - &spi_dw_data_port_1, &spi_dw_config_1, +DEVICE_AND_API_INIT(spi_dw_port_1, DT_INST_1_SNPS_DESIGNWARE_SPI_LABEL, + spi_dw_init, &spi_dw_data_port_1, &spi_dw_config_1, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &dw_spi_api); void spi_config_1_irq(void) { #ifdef CONFIG_SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(DT_SPI_DW_1_IRQ, DT_SPI_DW_1_IRQ_PRI, + IRQ_CONNECT(DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_0, + DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_0_PRIORITY, spi_dw_isr, DEVICE_GET(spi_dw_port_1), - DT_SPI_DW_1_IRQ_FLAGS); - irq_enable(DT_SPI_DW_1_IRQ); + DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_FLAGS); + irq_enable(DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_0); #else - IRQ_CONNECT(DT_SPI_DW_1_IRQ_RX_AVAIL, DT_SPI_DW_1_IRQ_RX_AVAIL_PRI, + IRQ_CONNECT(DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL, + DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), - DT_SPI_DW_1_IRQ_RX_AVAIL_FLAGS); - IRQ_CONNECT(DT_SPI_DW_1_IRQ_TX_REQ, DT_SPI_DW_1_IRQ_TX_REQ_PRI, + DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL_FLAGS); + IRQ_CONNECT(DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ, + DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), - DT_SPI_DW_IRQ_TX_REQ_FLAGS); - IRQ_CONNECT(DT_SPI_DW_1_IRQ_ERR_INT, DT_SPI_DW_1_IRQ_ERR_INT_PRI, + DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ_FLAGS); + IRQ_CONNECT(DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT, + DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), - DT_SPI_DW_IRQ_ERR_INT_FLAGS); + DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT_FLAGS); - irq_enable(DT_SPI_DW_1_IRQ_RX_AVAIL); - irq_enable(DT_SPI_DW_1_IRQ_TX_REQ); - irq_enable(DT_SPI_DW_1_IRQ_ERR_INT); + irq_enable(DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL); + irq_enable(DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ); + irq_enable(DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT); #endif } @@ -641,9 +665,17 @@ struct spi_dw_data spi_dw_data_port_2 = { SPI_CONTEXT_INIT_SYNC(spi_dw_data_port_2, ctx), }; +#ifdef DT_INST_2_SNPS_DESIGNWARE_SPI_CLOCKS_CLOCK_FREQUENCY +#define INST_2_SNPS_DESIGNWARE_SPI_CLOCK_FREQ \ + DT_INST_2_SNPS_DESIGNWARE_SPI_CLOCKS_CLOCK_FREQUENCY +#else +#define INST_2_SNPS_DESIGNWARE_SPI_CLOCK_FREQ \ + DT_INST_2_SNPS_DESIGNWARE_SPI_CLOCK_FREQUENCY +#endif + static const struct spi_dw_config spi_dw_config_2 = { - .regs = DT_SPI_DW_2_BASE_ADDRESS, - .clock_frequency = DT_SPI_DW_2_CLOCK_FREQUENCY, + .regs = DT_INST_2_SNPS_DESIGNWARE_SPI_BASE_ADDRESS, + .clock_frequency = INST_2_SNPS_DESIGNWARE_SPI_CLOCK_FREQ, #ifdef CONFIG_SPI_DW_PORT_2_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_2_CLOCK_GATE_SUBSYS), @@ -652,32 +684,36 @@ static const struct spi_dw_config spi_dw_config_2 = { .op_modes = CONFIG_SPI_2_OP_MODES }; -DEVICE_AND_API_INIT(spi_dw_port_2, DT_SPI_DW_2_NAME, spi_dw_init, - &spi_dw_data_port_2, &spi_dw_config_2, +DEVICE_AND_API_INIT(spi_dw_port_2, DT_INST_2_SNPS_DESIGNWARE_SPI_LABEL, + spi_dw_init, &spi_dw_data_port_2, &spi_dw_config_2, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &dw_spi_api); void spi_config_2_irq(void) { #ifdef CONFIG_SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(DT_SPI_DW_2_IRQ, DT_SPI_DW_2_IRQ_PRI, + IRQ_CONNECT(DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_0, + DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_0_PRIORITY, spi_dw_isr, DEVICE_GET(spi_dw_port_2), - DT_SPI_DW_2_IRQ_FLAGS); - irq_enable(DT_SPI_DW_2_IRQ); + DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_FLAGS); + irq_enable(DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_0); #else - IRQ_CONNECT(DT_SPI_DW_2_IRQ_RX_AVAIL, DT_SPI_DW_2_IRQ_RX_AVAIL_PRI, + IRQ_CONNECT(DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL, + DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_2), - DT_SPI_DW_2_IRQ_RX_AVAIL_FLAGS); - IRQ_CONNECT(DT_SPI_DW_2_IRQ_TX_REQ, DT_SPI_DW_2_IRQ_TX_REQ_PRI, + DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL_FLAGS); + IRQ_CONNECT(DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ, + DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_2), - DT_SPI_DW_2_IRQ_TX_REQ_FLAGS); - IRQ_CONNECT(DT_SPI_DW_2_IRQ_ERR_INT, DT_SPI_DW_2_IRQ_ERR_INT_PRI, + DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ_FLAGS); + IRQ_CONNECT(DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT, + DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_2), - DT_SPI_DW_2_IRQ_ERR_INT_FLAGS); + DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT_FLAGS); - irq_enable(DT_SPI_DW_2_IRQ_RX_AVAIL); - irq_enable(DT_SPI_DW_2_IRQ_TX_REQ); - irq_enable(DT_SPI_DW_2_IRQ_ERR_INT); + irq_enable(DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL); + irq_enable(DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ); + irq_enable(DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT); #endif } @@ -690,9 +726,17 @@ struct spi_dw_data spi_dw_data_port_3 = { SPI_CONTEXT_INIT_SYNC(spi_dw_data_port_3, ctx), }; +#ifdef DT_INST_3_SNPS_DESIGNWARE_SPI_CLOCKS_CLOCK_FREQUENCY +#define INST_3_SNPS_DESIGNWARE_SPI_CLOCK_FREQ \ + DT_INST_3_SNPS_DESIGNWARE_SPI_CLOCKS_CLOCK_FREQUENCY +#else +#define INST_3_SNPS_DESIGNWARE_SPI_CLOCK_FREQ \ + DT_INST_3_SNPS_DESIGNWARE_SPI_CLOCK_FREQUENCY +#endif + static const struct spi_dw_config spi_dw_config_3 = { - .regs = DT_SPI_DW_3_BASE_ADDRESS, - .clock_frequency = DT_SPI_DW_3_CLOCK_FREQUENCY, + .regs = DT_INST_3_SNPS_DESIGNWARE_SPI_BASE_ADDRESS, + .clock_frequency = INST_3_SNPS_DESIGNWARE_SPI_CLOCK_FREQ, #ifdef CONFIG_SPI_DW_PORT_3_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_3_CLOCK_GATE_SUBSYS), @@ -701,32 +745,36 @@ static const struct spi_dw_config spi_dw_config_3 = { .op_modes = CONFIG_SPI_3_OP_MODES }; -DEVICE_AND_API_INIT(spi_dw_port_3, DT_SPI_DW_3_NAME, spi_dw_init, - &spi_dw_data_port_3, &spi_dw_config_3, +DEVICE_AND_API_INIT(spi_dw_port_3, DT_INST_3_SNPS_DESIGNWARE_SPI_LABEL, + spi_dw_init, &spi_dw_data_port_3, &spi_dw_config_3, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &dw_spi_api); void spi_config_3_irq(void) { #ifdef CONFIG_SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(DT_SPI_DW_3_IRQ, DT_SPI_DW_3_IRQ_PRI, + IRQ_CONNECT(DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_0, + DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_0_PRIORITY, spi_dw_isr, DEVICE_GET(spi_dw_port_3), - DT_SPI_DW_3_IRQ_FLAGS); - irq_enable(DT_SPI_DW_3_IRQ); + DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_FLAGS); + irq_enable(DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_0); #else - IRQ_CONNECT(DT_SPI_DW_3_IRQ_RX_AVAIL, DT_SPI_DW_3_IRQ_RX_AVAIL_PRI, + IRQ_CONNECT(DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL, + DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), - DT_SPI_DW_3_IRQ_RX_AVAIL_FLAGS); - IRQ_CONNECT(DT_SPI_DW_3_IRQ_TX_REQ, DT_SPI_DW_3_IRQ_TX_REQ_PRI, + DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL_FLAGS); + IRQ_CONNECT(DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ, + DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), - DT_SPI_DW_3_IRQ_TX_REQ_FLAGS); - IRQ_CONNECT(DT_SPI_DW_3_IRQ_ERR_INT, DT_SPI_DW_3_IRQ_ERR_INT_PRI, + DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ_FLAGS); + IRQ_CONNECT(DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT, + DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), - DT_SPI_DW_3_IRQ_ERR_INT_FLAGS); + DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT_FLAGS); - irq_enable(DT_SPI_DW_3_IRQ_RX_AVAIL); - irq_enable(DT_SPI_DW_3_IRQ_TX_REQ); - irq_enable(DT_SPI_DW_3_IRQ_ERR_INT); + irq_enable(DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_RX_AVAIL); + irq_enable(DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_TX_REQ); + irq_enable(DT_INST_3_SNPS_DESIGNWARE_SPI_IRQ_ERR_INT); #endif } diff --git a/soc/arc/snps_arc_hsdk/dts_fixup.h b/soc/arc/snps_arc_hsdk/dts_fixup.h index 1a7f35d3bd3..e78d4866e5a 100644 --- a/soc/arc/snps_arc_hsdk/dts_fixup.h +++ b/soc/arc/snps_arc_hsdk/dts_fixup.h @@ -25,39 +25,8 @@ * SPI configuration */ -#define DT_SPI_DW_0_BASE_ADDRESS \ - DT_SNPS_DESIGNWARE_SPI_F0020000_BASE_ADDRESS -#define DT_SPI_DW_0_CLOCK_FREQUENCY \ - DT_SNPS_DESIGNWARE_SPI_F0020000_CLOCK_FREQUENCY -#define DT_SPI_DW_0_NAME DT_SNPS_DESIGNWARE_SPI_F0020000_LABEL -#define DT_SPI_DW_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0020000_IRQ_0 -#define DT_SPI_DW_0_IRQ_PRI \ - DT_SNPS_DESIGNWARE_SPI_F0020000_IRQ_0_PRIORITY -#define DT_SPI_DW_0_IRQ_FLAGS 0 - - -#define DT_SPI_DW_1_BASE_ADDRESS \ - DT_SNPS_DESIGNWARE_SPI_F0021000_BASE_ADDRESS -#define DT_SPI_DW_1_CLOCK_FREQUENCY \ - DT_SNPS_DESIGNWARE_SPI_F0021000_CLOCK_FREQUENCY -#define DT_SPI_DW_1_NAME DT_SNPS_DESIGNWARE_SPI_F0021000_LABEL -#define DT_SPI_DW_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0021000_IRQ_0 -#define DT_SPI_DW_1_IRQ_PRI \ - DT_SNPS_DESIGNWARE_SPI_F0021000_IRQ_0_PRIORITY -#define DT_SPI_DW_1_IRQ_FLAGS 0 - - -#define DT_SPI_DW_2_BASE_ADDRESS \ - DT_SNPS_DESIGNWARE_SPI_F0022000_BASE_ADDRESS -#define DT_SPI_DW_2_CLOCK_FREQUENCY \ - DT_SNPS_DESIGNWARE_SPI_F0022000_CLOCK_FREQUENCY -#define DT_SPI_DW_2_NAME DT_SNPS_DESIGNWARE_SPI_F0022000_LABEL -#define DT_SPI_DW_2_IRQ DT_SNPS_DESIGNWARE_SPI_F0022000_IRQ_0 -#define DT_SPI_DW_2_IRQ_PRI \ - DT_SNPS_DESIGNWARE_SPI_F0022000_IRQ_0_PRIORITY -#define DT_SPI_DW_2_IRQ_FLAGS 0 - -/* For spi_fujistu_fram sample */ -#define DT_SPI_1_NAME DT_SPI_DW_1_NAME +#define DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_FLAGS 0 +#define DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_FLAGS 0 +#define DT_INST_2_SNPS_DESIGNWARE_SPI_IRQ_FLAGS 0 /* End of SoC Level DTS fixup file */ diff --git a/soc/arc/snps_emsk/dts_fixup.h b/soc/arc/snps_emsk/dts_fixup.h index 0d7baf8f1bd..87b91857b11 100644 --- a/soc/arc/snps_emsk/dts_fixup.h +++ b/soc/arc/snps_emsk/dts_fixup.h @@ -48,27 +48,7 @@ * SPI configuration */ -#define DT_SPI_DW_0_BASE_ADDRESS \ - DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS -#define DT_SPI_DW_0_CLOCK_FREQUENCY \ - DT_SNPS_DESIGNWARE_SPI_F0006000_CLOCKS_CLOCK_FREQUENCY -#define DT_SPI_DW_0_NAME DT_SNPS_DESIGNWARE_SPI_F0006000_LABEL -#define DT_SPI_DW_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0 -#define DT_SPI_DW_0_IRQ_PRI \ - DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY -#define DT_SPI_DW_0_IRQ_FLAGS 0 - -#define DT_SPI_DW_1_BASE_ADDRESS \ - DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS -#define DT_SPI_DW_1_CLOCK_FREQUENCY \ - DT_SNPS_DESIGNWARE_SPI_F0007000_CLOCKS_CLOCK_FREQUENCY -#define DT_SPI_DW_1_NAME DT_SNPS_DESIGNWARE_SPI_F0007000_LABEL -#define DT_SPI_DW_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0 -#define DT_SPI_DW_1_IRQ_PRI \ - DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY -#define DT_SPI_DW_1_IRQ_FLAGS 0 - -/* For spi_fujistu_fram sample */ -#define DT_SPI_1_NAME DT_SPI_DW_1_NAME +#define DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_FLAGS 0 +#define DT_INST_1_SNPS_DESIGNWARE_SPI_IRQ_FLAGS 0 /* End of SoC Level DTS fixup file */ diff --git a/soc/arc/snps_emsk/soc.h b/soc/arc/snps_emsk/soc.h index 8b3f391e27b..03f32a3389f 100644 --- a/soc/arc/snps_emsk/soc.h +++ b/soc/arc/snps_emsk/soc.h @@ -62,9 +62,6 @@ #define DT_I2C_1_BASE_ADDR 0xF0005000 #define DT_I2C_1_IRQ_FLAGS 0 -/* SPI */ -#define DT_SPI_DW_IRQ_FLAGS 0 - /* * SPI Chip Select Assignments on EM Starter Kit * diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h index 5288ed5ec64..07ffbdc6dae 100644 --- a/soc/xtensa/intel_s1000/dts_fixup.h +++ b/soc/xtensa/intel_s1000/dts_fixup.h @@ -45,18 +45,7 @@ DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE #define DT_INTC_DW_0_NUM_IRQS DT_SNPS_DESIGNWARE_INTC_81800_NUM_IRQS -#define DT_SPI_DW_0_BASE_ADDRESS \ - DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS -#define DT_SPI_DW_0_CLOCK_FREQUENCY \ - DT_SNPS_DESIGNWARE_SPI_E000_CLOCKS_CLOCK_FREQUENCY -#define DT_SPI_DW_0_NAME \ - DT_SNPS_DESIGNWARE_SPI_E000_LABEL -#define DT_SPI_DW_0_IRQ \ - DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0 -#define DT_SPI_DW_0_IRQ_FLAGS \ - DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE -#define DT_SPI_DW_0_IRQ_PRI \ - DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY +#define DT_INST_0_SNPS_DESIGNWARE_SPI_IRQ_FLAGS 0 #define DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0