drivers: serial: Add UART driver for Renesas RA series
Adding initial support for Renesas RA UART. To avoid complicating initial code for supporting the SoC, I have implemented only the bare minimum for now. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
This commit is contained in:
TOKITA Hiroshi
Fabio Baltieri
parent
3292c36115
commit
69a3930a19
8 changed files with 505 additions and 0 deletions
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@ -66,6 +66,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_EFINIX_SAPPIHIRE uart_efinix_sapphire.c
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zephyr_library_sources_ifdef(CONFIG_UART_SEDI uart_sedi.c)
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zephyr_library_sources_ifdef(CONFIG_UART_BCM2711_MU uart_bcm2711.c)
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zephyr_library_sources_ifdef(CONFIG_UART_INTEL_LW uart_intel_lw.c)
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zephyr_library_sources_ifdef(CONFIG_UART_RA uart_ra.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c)
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@ -245,4 +245,6 @@ source "drivers/serial/Kconfig.bcm2711"
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source "drivers/serial/Kconfig.intel_lw"
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source "drivers/serial/Kconfig.ra"
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endif # SERIAL
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11
drivers/serial/Kconfig.ra
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11
drivers/serial/Kconfig.ra
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@ -0,0 +1,11 @@
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# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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# SPDX-License-Identifier: Apache-2.0
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config UART_RA
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bool "Renesas RA Series UART Driver"
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default y
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depends on DT_HAS_RENESAS_RA_UART_SCI_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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help
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Enable Renesas RA series UART driver.
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395
drivers/serial/uart_ra.c
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395
drivers/serial/uart_ra.c
Normal file
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@ -0,0 +1,395 @@
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/*
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* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_ra_uart_sci
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(ra_uart_sci, CONFIG_UART_LOG_LEVEL);
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struct uart_ra_cfg {
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mem_addr_t regs;
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const struct device *clock_dev;
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clock_control_subsys_t clock_id;
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const struct pinctrl_dev_config *pcfg;
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};
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struct uart_ra_data {
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struct uart_config current_config;
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uint32_t clk_rate;
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struct k_spinlock lock;
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};
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#define REG_MASK(reg) (BIT_MASK(_CONCAT(reg, _LEN)) << _CONCAT(reg, _POS))
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/* Registers */
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#define SMR 0x00 /*!< Serial Mode Register */
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#define BRR 0x01 /*!< Bit Rate Register */
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#define SCR 0x02 /*!< Serial Control Register */
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#define TDR 0x03 /*!< Transmit Data Register */
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#define SSR 0x04 /*!< Serial Status Register */
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#define RDR 0x05 /*!< Receive Data Register */
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#define SEMR 0x07 /*!< Serial Extended Mode Register */
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#define MDDR 0x12 /*!< Modulation Duty Register */
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#define LSR 0x18 /*!< Line Status Register */
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/*
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* SMR (Serial Mode Register)
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*
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* - CKS[0..2]: Clock Select
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* - MP[2..3]: Multi-Processor Mode(Valid only in asynchronous mode)
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* - STOP[3..4]: Stop Bit Length(Valid only in asynchronous mode)
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* - PM[4..5]: Parity Mode (Valid only when the PE bit is 1)
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* - PE[5..6]: Parity Enable(Valid only in asynchronous mode)
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* - CHR[6..7]: Character Length(Valid only in asynchronous mode)
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* - CM[7..8]: Communication Mode
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*/
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#define SMR_CKS_POS (0)
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#define SMR_CKS_LEN (2)
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#define SMR_MP_POS (2)
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#define SMR_MP_LEN (1)
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#define SMR_STOP_POS (3)
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#define SMR_STOP_LEN (1)
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#define SMR_PM_POS (4)
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#define SMR_PM_LEN (1)
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#define SMR_PE_POS (5)
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#define SMR_PE_LEN (1)
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#define SMR_CHR_POS (6)
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#define SMR_CHR_LEN (1)
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#define SMR_CM_POS (7)
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#define SMR_CM_LEN (1)
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/**
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* SCR (Serial Control Register)
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*
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* - CKE[0..2]: Clock Enable
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* - TEIE[2..3]: Transmit End Interrupt Enable
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* - MPIE[3..4]: Multi-Processor Interrupt Enable (Valid in asynchronous
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* - RE[4..5]: Receive Enable
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* - TE[5..6]: Transmit Enable
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* - RIE[6..7]: Receive Interrupt Enable
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* - TIE[7..8]: Transmit Interrupt Enable
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*/
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#define SCR_CKE_POS (0)
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#define SCR_CKE_LEN (2)
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#define SCR_TEIE_POS (2)
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#define SCR_TEIE_LEN (1)
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#define SCR_MPIE_POS (3)
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#define SCR_MPIE_LEN (1)
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#define SCR_RE_POS (4)
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#define SCR_RE_LEN (1)
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#define SCR_TE_POS (5)
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#define SCR_TE_LEN (1)
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#define SCR_RIE_POS (6)
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#define SCR_RIE_LEN (1)
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#define SCR_TIE_POS (7)
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#define SCR_TIE_LEN (1)
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/**
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* SSR (Serial Status Register)
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*
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* - MPBT[0..1]: Multi-Processor Bit Transfer
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* - MPB[1..2]: Multi-Processor
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* - TEND[2..3]: Transmit End Flag
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* - PER[3..4]: Parity Error Flag
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* - FER[4..5]: Framing Error Flag
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* - ORER[5..6]: Overrun Error Flag
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* - RDRF[6..7]: Receive Data Full Flag
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* - TDRE[7..8]: Transmit Data Empty Flag
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*/
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#define SSR_MPBT_POS (0)
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#define SSR_MPBT_LEN (1)
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#define SSR_MPB_POS (1)
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#define SSR_MPB_LEN (1)
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#define SSR_TEND_POS (2)
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#define SSR_TEND_LEN (1)
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#define SSR_PER_POS (3)
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#define SSR_PER_LEN (1)
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#define SSR_FER_POS (4)
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#define SSR_FER_LEN (1)
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#define SSR_ORER_POS (5)
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#define SSR_ORER_LEN (1)
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#define SSR_RDRF_POS (6)
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#define SSR_RDRF_LEN (1)
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#define SSR_TDRE_POS (7)
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#define SSR_TDRE_LEN (1)
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/**
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* SEMR (Serial Extended Mode Register)
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*
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* - ACS0[0..1]: Asynchronous Mode Clock Source Select
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* - PADIS[1..2]: Preamble function Disable
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* - BRME[2..3]: Bit Rate Modulation Enable
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* - ABCSE[3..4]: Asynchronous Mode Extended Base Clock Select
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* - ABCS[4..5]: Asynchronous Mode Base Clock Select
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* - NFEN[5..6]: Digital Noise Filter Function Enable
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* - BGDM[6..7]: Baud Rate Generator Double-Speed Mode Select
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* - RXDESEL[7..8]: Asynchronous Start Bit Edge Detection Select
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*/
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#define SEMR_ACS0_POS (0)
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#define SEMR_ACS0_LEN (1)
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#define SEMR_PADIS_POS (1)
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#define SEMR_PADIS_LEN (1)
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#define SEMR_BRME_POS (2)
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#define SEMR_BRME_LEN (1)
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#define SEMR_ABCSE_POS (3)
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#define SEMR_ABCSE_LEN (1)
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#define SEMR_ABCS_POS (4)
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#define SEMR_ABCS_LEN (1)
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#define SEMR_NFEN_POS (5)
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#define SEMR_NFEN_LEN (1)
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#define SEMR_BGDM_POS (6)
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#define SEMR_BGDM_LEN (1)
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#define SEMR_RXDESEL_POS (7)
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#define SEMR_RXDESEL_LEN (1)
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/**
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* LSR (Line Status Register)
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*
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* - ORER[0..1]: Overrun Error Flag
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* - FNUM[2..7]: Framing Error Count
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* - PNUM[8..13]: Parity Error Count
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*/
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#define LSR_ORER_POS (0)
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#define LSR_ORER_LEN (1)
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#define LSR_FNUM_POS (2)
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#define LSR_FNUM_LEN (5)
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#define LSR_PNUM_POS (8)
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#define LSR_PNUM_LEN (5)
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static uint8_t uart_ra_read_8(const struct device *dev,
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uint32_t offs)
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{
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const struct uart_ra_cfg *config = dev->config;
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return sys_read8(config->regs + offs);
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}
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static void uart_ra_write_8(const struct device *dev,
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uint32_t offs, uint8_t value)
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{
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const struct uart_ra_cfg *config = dev->config;
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sys_write8(value, config->regs + offs);
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}
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static uint16_t uart_ra_read_16(const struct device *dev,
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uint32_t offs)
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{
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const struct uart_ra_cfg *config = dev->config;
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return sys_read16(config->regs + offs);
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}
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static void uart_ra_write_16(const struct device *dev,
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uint32_t offs, uint16_t value)
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{
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const struct uart_ra_cfg *config = dev->config;
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sys_write16(value, config->regs + offs);
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}
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static void uart_ra_set_baudrate(const struct device *dev,
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uint32_t baud_rate)
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{
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struct uart_ra_data *data = dev->data;
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uint8_t reg_val;
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reg_val = uart_ra_read_8(dev, SEMR);
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reg_val |= REG_MASK(SEMR_BGDM);
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reg_val &= ~(REG_MASK(SEMR_BRME) | REG_MASK(SEMR_ABCSE) | REG_MASK(SEMR_ABCS));
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uart_ra_write_8(dev, SEMR, reg_val);
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reg_val = (data->clk_rate / (16 * data->current_config.baudrate)) - 1;
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uart_ra_write_8(dev, BRR, reg_val);
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}
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static int uart_ra_poll_in(const struct device *dev, unsigned char *p_char)
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{
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struct uart_ra_data *data = dev->data;
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int ret = 0;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {
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ret = -1;
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goto unlock;
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}
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*p_char = uart_ra_read_8(dev, RDR);
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unlock:
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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static void uart_ra_poll_out(const struct device *dev, unsigned char out_char)
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{
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struct uart_ra_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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uart_ra_write_8(dev, TDR, out_char);
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while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) ||
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!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) {
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;
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}
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k_spin_unlock(&data->lock, key);
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}
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static int uart_ra_configure(const struct device *dev,
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const struct uart_config *cfg)
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{
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struct uart_ra_data *data = dev->data;
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uint16_t reg_val;
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k_spinlock_key_t key;
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if (cfg->parity != UART_CFG_PARITY_NONE || cfg->stop_bits != UART_CFG_STOP_BITS_1 ||
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cfg->data_bits != UART_CFG_DATA_BITS_8 || cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
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return -ENOTSUP;
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}
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key = k_spin_lock(&data->lock);
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/* Disable Transmit and Receive */
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reg_val = uart_ra_read_8(dev, SCR);
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reg_val &= ~(REG_MASK(SCR_TE) | REG_MASK(SCR_RE));
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uart_ra_write_8(dev, SCR, reg_val);
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/* Resetting Errors Registers */
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reg_val = uart_ra_read_8(dev, SSR);
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reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER) |
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REG_MASK(SSR_RDRF) | REG_MASK(SSR_TDRE));
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uart_ra_write_8(dev, SSR, reg_val);
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reg_val = uart_ra_read_16(dev, LSR);
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reg_val &= ~(REG_MASK(LSR_ORER));
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uart_ra_write_16(dev, LSR, reg_val);
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/* Select internal clock */
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reg_val = uart_ra_read_8(dev, SCR);
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reg_val &= ~(REG_MASK(SCR_CKE));
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uart_ra_write_8(dev, SCR, reg_val);
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/* Serial Configuration (8N1) & Clock divider selection */
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reg_val = uart_ra_read_8(dev, SMR);
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reg_val &= ~(REG_MASK(SMR_CM) | REG_MASK(SMR_CHR) | REG_MASK(SMR_PE) | REG_MASK(SMR_PM) |
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REG_MASK(SMR_STOP) | REG_MASK(SMR_CKS));
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uart_ra_write_8(dev, SMR, reg_val);
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/* Set baudrate */
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uart_ra_set_baudrate(dev, cfg->baudrate);
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/* Enable Transmit & Receive + disable Interrupts */
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reg_val = uart_ra_read_8(dev, SCR);
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reg_val |= (REG_MASK(SCR_TE) | REG_MASK(SCR_RE));
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reg_val &=
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~(REG_MASK(SCR_TIE) | REG_MASK(SCR_RIE) | REG_MASK(SCR_MPIE) | REG_MASK(SCR_TEIE));
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uart_ra_write_8(dev, SCR, reg_val);
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data->current_config = *cfg;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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static int uart_ra_config_get(const struct device *dev,
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struct uart_config *cfg)
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{
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struct uart_ra_data *data = dev->data;
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*cfg = data->current_config;
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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static int uart_ra_init(const struct device *dev)
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{
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const struct uart_ra_cfg *config = dev->config;
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struct uart_ra_data *data = dev->data;
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int ret;
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/* Configure dt provided device signals when available */
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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if (!device_is_ready(config->clock_dev)) {
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return -ENODEV;
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}
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ret = clock_control_on(config->clock_dev, config->clock_id);
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if (ret < 0) {
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return ret;
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}
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ret = clock_control_get_rate(config->clock_dev, config->clock_id, &data->clk_rate);
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if (ret < 0) {
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return ret;
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}
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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ret = uart_ra_configure(dev, &data->current_config);
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if (ret != 0) {
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return ret;
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}
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return 0;
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}
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static const struct uart_driver_api uart_ra_driver_api = {
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.poll_in = uart_ra_poll_in,
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.poll_out = uart_ra_poll_out,
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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.configure = uart_ra_configure,
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.config_get = uart_ra_config_get,
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#endif
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};
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/* Device Instantiation */
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#define UART_RCAR_INIT_CFG(n) \
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PINCTRL_DT_DEFINE(DT_INST_PARENT(n)); \
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static const struct uart_ra_cfg uart_ra_cfg_##n = { \
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.regs = DT_REG_ADDR(DT_INST_PARENT(n)), \
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.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
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.clock_id = \
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(clock_control_subsys_t)DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, id), \
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.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)), \
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}
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#define UART_RCAR_INIT(n) \
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UART_RCAR_INIT_CFG(n); \
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\
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static struct uart_ra_data uart_ra_data_##n = { \
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.current_config = { \
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.baudrate = DT_INST_PROP(n, current_speed), \
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.parity = UART_CFG_PARITY_NONE, \
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.stop_bits = UART_CFG_STOP_BITS_1, \
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.data_bits = UART_CFG_DATA_BITS_8, \
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.flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
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}, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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uart_ra_init, \
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NULL, \
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&uart_ra_data_##n, \
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&uart_ra_cfg_##n, \
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PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
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&uart_ra_driver_api); \
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\
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DT_INST_FOREACH_STATUS_OKAY(UART_RCAR_INIT)
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||||
|
|
@ -245,6 +245,61 @@
|
|||
reg-names = "pfs", "pmisc_pwpr";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sci0: sci@40070000 {
|
||||
compatible = "renesas,ra-uart-sci";
|
||||
reg = <0x40070000 0x20>;
|
||||
interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_RXI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_TXI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_TEI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_ERI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_AM>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_RXI_OR_ERI>;
|
||||
interrupt-names = "rxi", "txi", "tei", "eri", "am", "rxi-or-eri";
|
||||
clocks = <&cgc RA_CLOCK_SCI(0)>;
|
||||
#clock-cells = <1>;
|
||||
status = "disabled";
|
||||
uart {
|
||||
compatible = "renesas,ra-uart-sci";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
sci1: sci@40070020 {
|
||||
compatible = "renesas,ra-uart-sci";
|
||||
reg = <0x40070020 0x20>;
|
||||
interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_RXI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_TXI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_TEI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_ERI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_AM>;
|
||||
interrupt-names = "rxi", "txi", "tei", "eri", "am";
|
||||
clocks = <&cgc RA_CLOCK_SCI(1)>;
|
||||
#clock-cells = <1>;
|
||||
status = "disabled";
|
||||
uart {
|
||||
compatible = "renesas,ra-uart-sci";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
sci9: sci@40070120 {
|
||||
compatible = "renesas,ra-uart-sci";
|
||||
reg = <0x40070120 0x20>;
|
||||
interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_RXI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_TXI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_TEI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_ERI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_AM>;
|
||||
interrupt-names = "rxi", "txi", "tei", "eri", "am";
|
||||
clocks = <&cgc RA_CLOCK_SCI(9)>;
|
||||
#clock-cells = <1>;
|
||||
status = "disabled";
|
||||
uart {
|
||||
compatible = "renesas,ra-uart-sci";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -43,5 +43,23 @@
|
|||
ngpios = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sci2: sci@40070040 {
|
||||
compatible = "renesas,ra-sci";
|
||||
reg = <0x40070040 0x20>;
|
||||
interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_RXI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_TXI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_TEI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_ERI>,
|
||||
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_AM>;
|
||||
interrupt-names = "rxi", "txi", "tei", "eri", "am";
|
||||
clocks = <&cgc RA_CLOCK_SCI(2)>;
|
||||
#clock-cells = <1>;
|
||||
status = "disabled";
|
||||
uart {
|
||||
compatible = "renesas,ra-uart-sci";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
15
dts/bindings/misc/renesas,ra-sci.yaml
Normal file
15
dts/bindings/misc/renesas,ra-sci.yaml
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Renesas RA SCI controller
|
||||
|
||||
compatible: "renesas,ra-sci"
|
||||
|
||||
include: [base.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
8
dts/bindings/serial/renesas,ra-uart-sci.yaml
Normal file
8
dts/bindings/serial/renesas,ra-uart-sci.yaml
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Renesas RA Series SCI based UART controller
|
||||
|
||||
compatible: "renesas,ra-uart-sci"
|
||||
|
||||
include: [uart-controller.yaml]
|
||||
Loading…
Add table
Add a link
Reference in a new issue