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x86: use MSRs for %gs

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We don't need to set up GDT data descriptors for setting
%gs. Instead, we use the x86 MSRs to set GS_BASE and
KERNEL_GS_BASE.

We don't currently allow user mode to set %gs on its own,
but later on if we do, we have everything set up to issue
'swapgs' instructions on syscall or IRQ.

Unused entries in the GDT have been removed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2019-11-12 17:56:21 -08:00 • committed by Anas Nashif
commit 692fda47fc
5 changed files with 40 additions and 75 deletions
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12
include/arch/x86/intel64/thread.h
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@ -17,14 +17,10 @@
#define X86_KERNEL_CS 0x18 /* 64-bit kernel code */
#define X86_KERNEL_DS 0x20 /* 64-bit kernel data */
#define X86_KERNEL_CPU0_GS 0x30 /* data selector covering TSS */
#define X86_KERNEL_CPU0_TR 0x40 /* 64-bit task state segment */
#define X86_KERNEL_CPU1_GS 0x50 /* data selector covering TSS */
#define X86_KERNEL_CPU1_TR 0x60 /* 64-bit task state segment */
#define X86_KERNEL_CPU2_GS 0x70 /* data selector covering TSS */
#define X86_KERNEL_CPU2_TR 0x80 /* 64-bit task state segment */
#define X86_KERNEL_CPU3_GS 0x90 /* data selector covering TSS */
#define X86_KERNEL_CPU3_TR 0xA0 /* 64-bit task state segment */
#define X86_KERNEL_CPU0_TR 0x28 /* 64-bit task state segment */
#define X86_KERNEL_CPU1_TR 0x38 /* 64-bit task state segment */
#define X86_KERNEL_CPU2_TR 0x48 /* 64-bit task state segment */
#define X86_KERNEL_CPU3_TR 0x58 /* 64-bit task state segment */
/*
* Some SSE definitions. Ideally these will ultimately be shared with 32-bit.