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soc: it8xxx2: optimize __soc_handle_irq and __soc_is_irq functions

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This reduces code size slightly.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li 2022-05-24 17:06:57 +08:00 • committed by Carles Cufí
commit 68fde3ceeb
1 changed files with 6 additions and 21 deletions
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27
soc/riscv/riscv-ite/common/soc_irq.S
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@ -20,17 +20,11 @@ GTEXT(__soc_handle_irq)
/* /*
* SOC-specific function to handle pending IRQ number generating the interrupt. * SOC-specific function to handle pending IRQ number generating the interrupt.
* Exception number is given as parameter via register a0. * Exception number is given as parameter via register a0.
* Jump to get_irq() function directly and return to caller by its
* ret instruction.
*/ */
SECTION_FUNC(exception.other, __soc_handle_irq) SECTION_FUNC(exception.other, __soc_handle_irq)
/* store ra */ j get_irq
addi sp, sp, -4
sw ra, 0(sp)
/* get interrupt number and clear interrupt status of soc */
call get_irq
/* restore ra */
lw ra, 0(sp)
addi sp, sp, 4
ret
/* /*
* __soc_is_irq is defined as .weak to allow re-implementation by * __soc_is_irq is defined as .weak to allow re-implementation by
@ -45,16 +39,7 @@ WTEXT(__soc_is_irq)
* *
*/ */
SECTION_FUNC(exception.other, __soc_is_irq) SECTION_FUNC(exception.other, __soc_is_irq)
/* Read mcause and check if interrupt bit is set */ /* Read mcause and check if interrupt bit (bit 31) is set */
csrr t0, mcause csrr a0, mcause
li t1, SOC_MCAUSE_IRQ_MASK srli a0, a0, 31
and t0, t0, t1
/* If interrupt bit is not set, return with 0 */
addi a0, x0, 0
beqz t0, not_interrupt
addi a0, a0, 1
not_interrupt:
/* return */
ret ret