diff --git a/dts/arm/nxp/nxp_kw2xd.dtsi b/dts/arm/nxp/nxp_kw2xd.dtsi index 47ab4552fa7..9df75053120 100644 --- a/dts/arm/nxp/nxp_kw2xd.dtsi +++ b/dts/arm/nxp/nxp_kw2xd.dtsi @@ -59,8 +59,28 @@ compatible = "nxp,kinetis-sim"; reg = <0x40047000 0x1060>; label = "SIM"; - #clock-cells = <3>; + + core_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <1>; + #clock-cells = <0>; + }; + + bus_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <1>; + #clock-cells = <0>; + }; + + flash_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <2>; + #clock-cells = <0>; + }; }; ftfl: flash-controller@40020000 { diff --git a/dts/arm/nxp/nxp_kw40z.dtsi b/dts/arm/nxp/nxp_kw40z.dtsi index 64e909d78c7..b51036326ce 100644 --- a/dts/arm/nxp/nxp_kw40z.dtsi +++ b/dts/arm/nxp/nxp_kw40z.dtsi @@ -3,6 +3,7 @@ #include #include "armv6-m.dtsi" #include +#include #include #include @@ -29,8 +30,10 @@ soc { mcg: clock-controller@40064000 { - compatible = "nxp,kw41z-mcg"; + compatible = "nxp,kinetis-mcg"; reg = <0x40064000 0x13>; + label = "MCG"; + #clock-cells = <1>; }; osc: clock-controller@40065000 { @@ -49,8 +52,21 @@ compatible = "nxp,kinetis-sim"; reg = <0x40047000 0x1060>; label = "SIM"; - #clock-cells = <3>; + + core_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <1>; + #clock-cells = <0>; + }; + + flash_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <2>; + #clock-cells = <0>; + }; }; ftfa: flash-controller@40020000 { diff --git a/dts/arm/nxp/nxp_kw41z.dtsi b/dts/arm/nxp/nxp_kw41z.dtsi index 91916b7b833..6bc94af0794 100644 --- a/dts/arm/nxp/nxp_kw41z.dtsi +++ b/dts/arm/nxp/nxp_kw41z.dtsi @@ -35,7 +35,7 @@ soc { mcg: clock-controller@40064000 { - compatible = "nxp,kw41z-mcg"; + compatible = "nxp,kinetis-mcg"; reg = <0x40064000 0x13>; label = "MCG"; #clock-cells = <1>; @@ -60,8 +60,21 @@ compatible = "nxp,kinetis-sim"; reg = <0x40047000 0x1060>; label = "SIM"; - #clock-cells = <3>; + + core_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <1>; + #clock-cells = <0>; + }; + + flash_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <2>; + #clock-cells = <0>; + }; }; ftfa: flash-controller@40020000 { diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.soc b/soc/arm/nxp_kinetis/kwx/Kconfig.soc index 6672a26a9af..bce1df4c9ef 100644 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.soc +++ b/soc/arm/nxp_kinetis/kwx/Kconfig.soc @@ -89,29 +89,4 @@ config SOC_PART_NUMBER_KINETIS_KWX that you should not set directly. The part number selection choice defines the default value for this string. -if SOC_MKW24D5 || SOC_MKW22D5 - -config KW2XD_CORE_CLOCK_DIVIDER - int "KW2xD core clock divider" - default 1 - help - This option specifies the divide value for the KW2xD processor core - clock from the system clock. - -config KW2XD_BUS_CLOCK_DIVIDER - int "KW2xD bus clock divider" - default 1 - help - This option specifies the divide value for the KW2xD bus clock from - the system clock. - -config KW2XD_FLASH_CLOCK_DIVIDER - int "KW2xD flash clock divider" - default 2 - help - This option specifies the divide value for the KW2xD flash clock from - the system clock. - -endif # SOC_MKW24D5 || SOC_MKW22D5 - endif # SOC_SERIES_KINETIS_KWX diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c index 00b415e1a44..c2facead3c4 100644 --- a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c +++ b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c @@ -26,6 +26,12 @@ #define TIMESRC_OSCERCLK (2) +#define CLOCK_NODEID(clk) \ + DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk) + +#define CLOCK_DIVIDER(clk) \ + DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1 + static const osc_config_t oscConfig = { .freq = CONFIG_OSC_XTAL0_FREQ, .capLoad = 0, @@ -58,9 +64,9 @@ static const mcg_pll_config_t pll0Config = { static const sim_clock_config_t simConfig = { .pllFllSel = PLLFLLSEL_MCGPLLCLK, /* PLLFLLSEL select PLL. */ .er32kSrc = ER32KSEL_RTC, /* ERCLK32K selection, use RTC. */ - .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_KW2XD_CORE_CLOCK_DIVIDER - 1) | - SIM_CLKDIV1_OUTDIV2(CONFIG_KW2XD_BUS_CLOCK_DIVIDER - 1) | - SIM_CLKDIV1_OUTDIV4(CONFIG_KW2XD_FLASH_CLOCK_DIVIDER - 1), + .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) | + SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) | + SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)), }; /** diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c b/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c index 222cf0c3ea4..a8d13fbc58a 100644 --- a/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c +++ b/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c @@ -16,7 +16,11 @@ #define LPUART0SRC_OSCERCLK (1) #define TPMSRC_MCGPLLCLK (1) -#define CLKDIV1_DIVBY2 (1) +#define CLOCK_NODEID(clk) \ + DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk) + +#define CLOCK_DIVIDER(clk) \ + DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1 static const osc_config_t oscConfig = { .freq = CONFIG_OSC_XTAL0_FREQ, @@ -34,7 +38,8 @@ static const osc_config_t oscConfig = { static const sim_clock_config_t simConfig = { .er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select), - .clkdiv1 = SIM_CLKDIV1_OUTDIV4(CLKDIV1_DIVBY2), + .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) | + SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)), }; /* This function comes from the MCUX SDK: