boards: arm: npcx: add support for npcx4m8f_evb

Add support for npcx4m8f_evb board that is a development platform to
evaluate the Nuvoton NPCX4 embedded controller.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Mulin Chao 2023-05-02 02:37:54 -07:00 committed by Carles Cufí
commit 68dd26574c
11 changed files with 405 additions and 0 deletions

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# Copyright (c) 2023 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
config BOARD_NPCX4M8F_EVB
bool "Nuvoton NPCX4M8F EVB Development board"
depends on SOC_NPCX4M8F

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# Copyright (c) 2023 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
if BOARD_NPCX4M8F_EVB
config BOARD
default "npcx4m8f_evb"
endif # BOARD_NPCX4M8F_EVB
config SYS_CLOCK_TICKS_PER_SEC
default 1000
config INPUT
default y if KSCAN

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# SPDX-License-Identifier: Apache-2.0
board_runner_args(openocd --cmd-load "npcx_write_image")
board_runner_args(openocd --cmd-verify "npcx_verify_image")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

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.. _npcx4m8f_evb:
Nuvoton NPCX4M8F_EVB
####################
Overview
********
The NPCX4M8F_EVB kit is a development platform to evaluate the
Nuvoton NPCX4 series microcontrollers. This board needs to be mated with
part number NPCX498F.
.. image:: npcx4m8f_evb.jpg
:align: center
:alt: NPCX4M8F Evaluation Board
Hardware
********
- ARM Cortex-M4F Processor
- 512 KB RAM and 64 KB boot ROM
- ADC & GPIO headers
- UART0 and UART1
- FAN PWM interface
- Jtag interface
- Intel Modular Embedded Controller Card (MECC) headers
Supported Features
==================
The following features are supported:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc controller |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c port/controller |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| PM | on-chip | power management |
+-----------+------------+-------------------------------------+
| PSL | on-chip | power switch logic |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pulse width modulator |
+-----------+------------+-------------------------------------+
| TACH | on-chip | tachometer sensor |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| WDT | on-chip | watchdog |
+-----------+------------+-------------------------------------+
Other hardware features are not currently supported by Zephyr (at the moment)
The default configuration can be found in the defconfig file:
``boards/arm/npcx4m8f_evb/npcx4m8f_evb_defconfig``
Connections and IOs
===================
Nuvoton to provide the schematic for this board.
System Clock
============
The NPCX4M8F MCU is configured to use the 120Mhz internal oscillator with the
on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock
control register (chapter 4 in user manual)
Serial Port
===========
UART1 is configured for serial logs.
Programming and Debugging
*************************
This board comes with a Cortex ETM port which facilitates tracing and debugging
using a single physical connection. In addition, it comes with sockets for
JTAG-only sessions.
Flashing
========
If the correct headers are installed, this board supports both J-TAG and also
the ChromiumOS servo.
To flash using Servo V2, μServo, or Servo V4 (CCD), see the
`Chromium EC Flashing Documentation`_ for more information.
To flash with J-TAG, install the drivers for your programmer, for example:
SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/
The openocd from Zephyr SDK 0.16.1 doesn't include npcx4 support, so build openocd from source.::
sudo apt-get install libftdi-dev libusb-1.0.0-dev
git clone https://git.code.sf.net/p/openocd/code ~/openocd
cd ~/openocd
./bootstrap
./configure --enable-jlink --enable-ftdi
make clean
make
sudo make install
Build and flash the blinky sample.::
west build -t clean && \
west build -c -p auto -b npcx4m8f_evb samples/basic/blinky && \
west flash --openocd /usr/local/bin/openocd
Debugging
=========
Use JTAG/SWD with a J-Link
References
**********
.. target-notes::
.. _Chromium EC Flashing Documentation:
https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board

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/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nuvoton/npcx/npcx4/npcx4-pinctrl.dtsi>
&i2c0_0_sda_scl_gpb4_b5 {
bias-pull-up; /* Enable internal pull-up for i2c0_0 */
pinmux-locked; /* Lock pinmuxing */
};
&pwm6_gpc0 {
drive-open-drain;
};

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/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nuvoton/npcx4m8f.dtsi>
#include "npcx4m8f_evb-pinctrl.dtsi"
/ {
model = "Nuvoton NPCX4M8F evaluation board";
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart1;
zephyr,flash = &flash0;
zephyr,keyboard-scan = &kscan_input;
};
aliases {
pwm-led0 = &pwm_led0_green;
led0 = &gpio_led_red;
pwm-0 = &pwm6;
i2c-0 = &i2c0_0;
watchdog0 = &twd0;
peci-0 = &peci0;
spi-flash0 = &int_flash;
kscan0 = &kscan_input;
};
leds-pwm {
compatible = "pwm-leds";
pwm_led0_green: pwm_led_0 {
pwms = <&pwm6 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "User D7 green";
};
};
leds-gpio {
compatible = "gpio-leds";
gpio_led_red: led_0 {
gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;
label = "User D8 red";
};
};
};
/* Overwrite default device properties with overlays in board dt file here. */
&uart1 {
status = "okay";
current-speed = <115200>;
/* Use UART1_SL2 ie. PIN64.65 */
pinctrl-0 = <&uart1_2_sin_gp64 &uart1_2_sout_gp65>;
pinctrl-names = "default";
};
&pwm6 {
status = "okay";
pinctrl-0 = <&pwm6_gpc0>;
pinctrl-names = "default";
};
&adc0 {
status = "okay";
/* Use adc0 channel 0 and 2 for 'adc_api' driver tests */
pinctrl-0 = <&adc0_chan0_gp45 &adc0_chan2_gp43>;
pinctrl-names = "default";
};
&espi0 {
status = "okay";
pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
pinctrl-names = "default";
};
&i2c0_0 {
status = "okay";
pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c_ctrl0 {
status = "okay";
};
&tach1 {
status = "okay";
pinctrl-0 = <&ta1_1_in_gp40>;
pinctrl-names = "default";
port = <NPCX_TACH_PORT_A>;
sample-clk = <NPCX_TACH_FREQ_LFCLK>;
pulses-per-round = <1>;
};
&peci0 {
status = "okay";
pinctrl-0 = <&peci_dat_gp81>;
pinctrl-names = "default";
};
&kbd {
/* Demonstrate a 13 x 8 keyboard matrix on evb */
pinctrl-0 = <&ksi0_gp31 &ksi1_gp30 &ksi2_gp27 &ksi3_gp26
&ksi4_gp25 &ksi5_gp24 &ksi6_gp23 &ksi7_gp22
&kso00_gp21 &kso01_gp20 &kso02_gp17 &kso03_gp16
&kso04_gp15 &kso05_gp14 &kso06_gp13 &kso07_gp12
&kso08_gp11 &kso09_gp10 &kso10_gp07 &kso11_gp06
&kso12_gp05>;
pinctrl-names = "default";
row-size = <8>;
col-size = <13>;
status = "okay";
kscan_input: kscan-input {
compatible = "zephyr,kscan-input";
};
};

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#
# Copyright (c) 2023 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
#
identifier: npcx4m8f_evb
name: Nuvoton NPCX4M8F EVB
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 114
flash: 384
supported:
- adc
- clock
- gpio
- i2c
- pm
- pwm
- psl
- tach
- uart
- watchdog

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#
# Copyright (c) 2023 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SOC_NPCX4M8F=y
CONFIG_SOC_SERIES_NPCX4=y
CONFIG_BOARD_NPCX4M8F_EVB=y
# Enable NPCX firmware header
CONFIG_NPCX_HEADER=y
CONFIG_NPCX_IMAGE_OUTPUT_HEX=y
CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y
CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y
# Enable MPU
CONFIG_ARM_MPU=y
# Clock configuration
CONFIG_CLOCK_CONTROL=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
# UART Driver
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# GPIO Driver
CONFIG_GPIO=y
# Pin Controller Driver
CONFIG_PINCTRL=y
# Console Driver
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

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# script for Nuvoton NPCX Cortex-M4 Series
source [find interface/jlink.cfg]
transport select swd
set FIUNAME npcx_v2.fiu
source [find target/npcx.cfg]
proc npcx_write_image {target_image} {
flash write_image erase $target_image 0x64000000 ihex
}
proc npcx_verify_image {target_image} {
verify_image $target_image 0x64000000 ihex
}

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/*
* Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
zephyr,user {
io-channels = <&adc0 0>, <&adc0 2>;
};
};
&adc0 {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <10>;
};
channel@2 {
reg = <2>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <10>;
};
};