drivers: adc: mcux_adc12: add driver for the NXP ADC12 module
Add MCUX driver shim for the NXP Kinetis 12-bit ADC module (ADC12). Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit is contained in:
parent
1c55882ae3
commit
683ca77620
7 changed files with 453 additions and 0 deletions
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@ -2,6 +2,7 @@
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zephyr_library()
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC12 adc_mcux_adc12.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC16 adc_mcux_adc16.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC16 adc_mcux_adc16.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_SAM_AFEC adc_sam_afec.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_SAM_AFEC adc_sam_afec.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c)
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@ -47,6 +47,9 @@ config ADC_0
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config ADC_1
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config ADC_1
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bool "Enable ADC 1"
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bool "Enable ADC 1"
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config ADC_2
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bool "Enable ADC 2"
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source "drivers/adc/Kconfig.mcux"
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source "drivers/adc/Kconfig.mcux"
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source "drivers/adc/Kconfig.nrfx"
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source "drivers/adc/Kconfig.nrfx"
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@ -6,6 +6,12 @@
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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#
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#
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config ADC_MCUX_ADC12
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bool "MCUX ADC12 driver"
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depends on HAS_MCUX_ADC12
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help
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Enable the MCUX ADC12 driver.
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config ADC_MCUX_ADC16
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config ADC_MCUX_ADC16
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bool "MCUX ADC16 driver"
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bool "MCUX ADC16 driver"
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depends on HAS_MCUX_ADC16
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depends on HAS_MCUX_ADC16
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382
drivers/adc/adc_mcux_adc12.c
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382
drivers/adc/adc_mcux_adc12.c
Normal file
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@ -0,0 +1,382 @@
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/*
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* Based on adc_mcux_adc16.c, which is:
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* Copyright (c) 2017-2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <adc.h>
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#include <fsl_adc12.h>
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#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(adc_mcux_adc12);
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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struct mcux_adc12_config {
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ADC_Type *base;
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adc12_clock_source_t clock_src;
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adc12_clock_divider_t clock_div;
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adc12_reference_voltage_source_t ref_src;
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uint32_t sample_clk_count;
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void (*irq_config_func)(struct device *dev);
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};
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struct mcux_adc12_data {
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struct device *dev;
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struct adc_context ctx;
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u16_t *buffer;
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u16_t *repeat_buffer;
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u32_t channels;
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u8_t channel_id;
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};
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static int mcux_adc12_channel_setup(struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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u8_t channel_id = channel_cfg->channel_id;
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if (channel_id > (ADC_SC1_ADCH_MASK >> ADC_SC1_ADCH_SHIFT)) {
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LOG_ERR("Invalid channel %d", channel_id);
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return -EINVAL;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Unsupported channel acquisition time");
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return -ENOTSUP;
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}
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if (channel_cfg->differential) {
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LOG_ERR("Differential channels are not supported");
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return -ENOTSUP;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Unsupported channel gain %d", channel_cfg->gain);
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return -ENOTSUP;
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}
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if (channel_cfg->reference != ADC_REF_INTERNAL) {
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LOG_ERR("Unsupported channel reference");
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return -ENOTSUP;
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}
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return 0;
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}
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static int mcux_adc12_start_read(struct device *dev,
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const struct adc_sequence *sequence)
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{
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const struct mcux_adc12_config *config = dev->config->config_info;
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struct mcux_adc12_data *data = dev->driver_data;
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adc12_hardware_average_mode_t mode;
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adc12_resolution_t resolution;
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ADC_Type *base = config->base;
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int error;
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u32_t tmp32;
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switch (sequence->resolution) {
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case 8:
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resolution = kADC12_Resolution8Bit;
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break;
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case 10:
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resolution = kADC12_Resolution10Bit;
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break;
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case 12:
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resolution = kADC12_Resolution12Bit;
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break;
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default:
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LOG_ERR("Unsupported resolution %d", sequence->resolution);
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return -ENOTSUP;
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}
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tmp32 = base->CFG1 & ~(ADC_CFG1_MODE_MASK);
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tmp32 |= ADC_CFG1_MODE(resolution);
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base->CFG1 = tmp32;
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switch (sequence->oversampling) {
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case 0:
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mode = kADC12_HardwareAverageDisabled;
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break;
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case 2:
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mode = kADC12_HardwareAverageCount4;
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break;
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case 3:
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mode = kADC12_HardwareAverageCount8;
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break;
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case 4:
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mode = kADC12_HardwareAverageCount16;
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break;
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case 5:
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mode = kADC12_HardwareAverageCount32;
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break;
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default:
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LOG_ERR("Unsupported oversampling value %d",
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sequence->oversampling);
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return -ENOTSUP;
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}
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ADC12_SetHardwareAverage(config->base, mode);
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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error = adc_context_wait_for_completion(&data->ctx);
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return error;
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}
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static int mcux_adc12_read_async(struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct mcux_adc12_data *data = dev->driver_data;
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int error;
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adc_context_lock(&data->ctx, async ? true : false, async);
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error = mcux_adc12_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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static int mcux_adc12_read(struct device *dev,
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const struct adc_sequence *sequence)
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{
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return mcux_adc12_read_async(dev, sequence, NULL);
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}
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static void mcux_adc12_start_channel(struct device *dev)
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{
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const struct mcux_adc12_config *config = dev->config->config_info;
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struct mcux_adc12_data *data = dev->driver_data;
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adc12_channel_config_t channel_config;
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u32_t channel_group = 0U;
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data->channel_id = find_lsb_set(data->channels) - 1;
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LOG_DBG("Starting channel %d", data->channel_id);
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channel_config.enableInterruptOnConversionCompleted = true;
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channel_config.channelNumber = data->channel_id;
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ADC12_SetChannelConfig(config->base, channel_group, &channel_config);
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct mcux_adc12_data *data =
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CONTAINER_OF(ctx, struct mcux_adc12_data, ctx);
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data->channels = ctx->sequence.channels;
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data->repeat_buffer = data->buffer;
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mcux_adc12_start_channel(data->dev);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct mcux_adc12_data *data =
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CONTAINER_OF(ctx, struct mcux_adc12_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static void mcux_adc12_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct mcux_adc12_config *config = dev->config->config_info;
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struct mcux_adc12_data *data = dev->driver_data;
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ADC_Type *base = config->base;
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u32_t channel_group = 0U;
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u16_t result;
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result = ADC12_GetChannelConversionValue(base, channel_group);
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LOG_DBG("Finished channel %d. Result is 0x%04x",
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data->channel_id, result);
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*data->buffer++ = result;
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data->channels &= ~BIT(data->channel_id);
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if (data->channels) {
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mcux_adc12_start_channel(dev);
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} else {
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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static int mcux_adc12_init(struct device *dev)
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{
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const struct mcux_adc12_config *config = dev->config->config_info;
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struct mcux_adc12_data *data = dev->driver_data;
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ADC_Type *base = config->base;
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adc12_config_t adc_config;
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ADC12_GetDefaultConfig(&adc_config);
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adc_config.referenceVoltageSource = config->ref_src;
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adc_config.clockSource = config->clock_src;
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adc_config.clockDivider = config->clock_div;
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adc_config.sampleClockCount = config->sample_clk_count;
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adc_config.resolution = kADC12_Resolution12Bit;
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adc_config.enableContinuousConversion = false;
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ADC12_Init(base, &adc_config);
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ADC12_DoAutoCalibration(base);
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ADC12_EnableHardwareTrigger(base, false);
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config->irq_config_func(dev);
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data->dev = dev;
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct adc_driver_api mcux_adc12_driver_api = {
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.channel_setup = mcux_adc12_channel_setup,
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.read = mcux_adc12_read,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = mcux_adc12_read_async,
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#endif
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};
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#define ASSERT_WITHIN_RANGE(val, min, max, str) \
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BUILD_ASSERT_MSG(val >= min && val <= max, str)
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#define ASSERT_ADC12_CLK_DIV_VALID(val, str) \
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BUILD_ASSERT_MSG(val == 1 || val == 2 || val == 4 || val == 8, str)
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#define TO_ADC12_CLOCK_SRC(val) _DO_CONCAT(kADC12_ClockSourceAlt, val)
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#define TO_ADC12_CLOCK_DIV(val) _DO_CONCAT(kADC12_ClockDivider, val)
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#if CONFIG_ADC_0
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static void mcux_adc12_config_func_0(struct device *dev);
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_ADC12_ADC_0_CLK_SOURCE, 0, 3,
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"Invalid clock source");
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ASSERT_ADC12_CLK_DIV_VALID(DT_NXP_KINETIS_ADC12_ADC_0_CLK_DIVIDER,
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"Invalid clock divider");
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_ADC12_ADC_0_SAMPLE_TIME, 2, 256,
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"Invalid sample time");
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static const struct mcux_adc12_config mcux_adc12_config_0 = {
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.base = (ADC_Type *)DT_NXP_KINETIS_ADC12_ADC_0_BASE_ADDRESS,
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.clock_src = TO_ADC12_CLOCK_SRC(DT_NXP_KINETIS_ADC12_ADC_0_CLK_SOURCE),
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.clock_div = TO_ADC12_CLOCK_DIV(DT_NXP_KINETIS_ADC12_ADC_0_CLK_DIVIDER),
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#if DT_NXP_KINETIS_ADC12_ADC_0_ALTERNATE_VOLTAGE_REFERENCE == 1
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.ref_src = kADC12_ReferenceVoltageSourceValt,
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#else
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.ref_src = kADC12_ReferenceVoltageSourceVref,
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#endif
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.sample_clk_count = DT_NXP_KINETIS_ADC12_ADC_0_SAMPLE_TIME,
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.irq_config_func = mcux_adc12_config_func_0,
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};
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static struct mcux_adc12_data mcux_adc12_data_0 = {
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ADC_CONTEXT_INIT_TIMER(mcux_adc12_data_0, ctx),
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ADC_CONTEXT_INIT_LOCK(mcux_adc12_data_0, ctx),
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ADC_CONTEXT_INIT_SYNC(mcux_adc12_data_0, ctx),
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};
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DEVICE_AND_API_INIT(mcux_adc12_0, DT_NXP_KINETIS_ADC12_ADC_0_LABEL,
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&mcux_adc12_init, &mcux_adc12_data_0, &mcux_adc12_config_0,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&mcux_adc12_driver_api);
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static void mcux_adc12_config_func_0(struct device *dev)
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{
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IRQ_CONNECT(DT_NXP_KINETIS_ADC12_ADC_0_IRQ,
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DT_NXP_KINETIS_ADC12_ADC_0_IRQ_PRIORITY, mcux_adc12_isr,
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DEVICE_GET(mcux_adc12_0), 0);
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irq_enable(DT_NXP_KINETIS_ADC12_ADC_0_IRQ);
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}
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#endif /* CONFIG_ADC_0 */
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#if CONFIG_ADC_1
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static void mcux_adc12_config_func_1(struct device *dev);
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_ADC12_ADC_1_CLK_SOURCE, 0, 3,
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"Invalid clock source");
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ASSERT_ADC12_CLK_DIV_VALID(DT_NXP_KINETIS_ADC12_ADC_1_CLK_DIVIDER,
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"Invalid clock divider");
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_ADC12_ADC_1_SAMPLE_TIME, 2, 256,
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"Invalid sample time");
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static const struct mcux_adc12_config mcux_adc12_config_1 = {
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.base = (ADC_Type *)DT_NXP_KINETIS_ADC12_ADC_1_BASE_ADDRESS,
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.clock_src = TO_ADC12_CLOCK_SRC(DT_NXP_KINETIS_ADC12_ADC_1_CLK_SOURCE),
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.clock_div = TO_ADC12_CLOCK_DIV(DT_NXP_KINETIS_ADC12_ADC_1_CLK_DIVIDER),
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#if DT_NXP_KINETIS_ADC12_ADC_1_ALTERNATE_VOLTAGE_REFERENCE == 1
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.ref_src = kADC12_ReferenceVoltageSourceValt,
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#else
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||||||
|
.ref_src = kADC12_ReferenceVoltageSourceVref,
|
||||||
|
#endif
|
||||||
|
.sample_clk_count = DT_NXP_KINETIS_ADC12_ADC_1_SAMPLE_TIME,
|
||||||
|
.irq_config_func = mcux_adc12_config_func_1,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct mcux_adc12_data mcux_adc12_data_1 = {
|
||||||
|
ADC_CONTEXT_INIT_TIMER(mcux_adc12_data_1, ctx),
|
||||||
|
ADC_CONTEXT_INIT_LOCK(mcux_adc12_data_1, ctx),
|
||||||
|
ADC_CONTEXT_INIT_SYNC(mcux_adc12_data_1, ctx),
|
||||||
|
};
|
||||||
|
|
||||||
|
DEVICE_AND_API_INIT(mcux_adc12_1, DT_NXP_KINETIS_ADC12_ADC_1_LABEL,
|
||||||
|
&mcux_adc12_init, &mcux_adc12_data_1, &mcux_adc12_config_1,
|
||||||
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||||
|
&mcux_adc12_driver_api);
|
||||||
|
|
||||||
|
static void mcux_adc12_config_func_1(struct device *dev)
|
||||||
|
{
|
||||||
|
IRQ_CONNECT(DT_NXP_KINETIS_ADC12_ADC_1_IRQ,
|
||||||
|
DT_NXP_KINETIS_ADC12_ADC_1_IRQ_PRIORITY, mcux_adc12_isr,
|
||||||
|
DEVICE_GET(mcux_adc12_1), 0);
|
||||||
|
|
||||||
|
irq_enable(DT_NXP_KINETIS_ADC12_ADC_1_IRQ);
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_ADC_1 */
|
||||||
|
|
||||||
|
#if CONFIG_ADC_2
|
||||||
|
static void mcux_adc12_config_func_2(struct device *dev);
|
||||||
|
|
||||||
|
ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_ADC12_ADC_2_CLK_SOURCE, 0, 3,
|
||||||
|
"Invalid clock source");
|
||||||
|
ASSERT_ADC12_CLK_DIV_VALID(DT_NXP_KINETIS_ADC12_ADC_2_CLK_DIVIDER,
|
||||||
|
"Invalid clock divider");
|
||||||
|
ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_ADC12_ADC_2_SAMPLE_TIME, 2, 256,
|
||||||
|
"Invalid sample time");
|
||||||
|
static const struct mcux_adc12_config mcux_adc12_config_2 = {
|
||||||
|
.base = (ADC_Type *)DT_NXP_KINETIS_ADC12_ADC_2_BASE_ADDRESS,
|
||||||
|
.clock_src = TO_ADC12_CLOCK_SRC(DT_NXP_KINETIS_ADC12_ADC_2_CLK_SOURCE),
|
||||||
|
.clock_div = TO_ADC12_CLOCK_DIV(DT_NXP_KINETIS_ADC12_ADC_2_CLK_DIVIDER),
|
||||||
|
#if DT_NXP_KINETIS_ADC12_ADC_2_ALTERNATE_VOLTAGE_REFERENCE == 1
|
||||||
|
.ref_src = kADC12_ReferenceVoltageSourceValt,
|
||||||
|
#else
|
||||||
|
.ref_src = kADC12_ReferenceVoltageSourceVref,
|
||||||
|
#endif
|
||||||
|
.sample_clk_count = DT_NXP_KINETIS_ADC12_ADC_2_SAMPLE_TIME,
|
||||||
|
.irq_config_func = mcux_adc12_config_func_2,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct mcux_adc12_data mcux_adc12_data_2 = {
|
||||||
|
ADC_CONTEXT_INIT_TIMER(mcux_adc12_data_2, ctx),
|
||||||
|
ADC_CONTEXT_INIT_LOCK(mcux_adc12_data_2, ctx),
|
||||||
|
ADC_CONTEXT_INIT_SYNC(mcux_adc12_data_2, ctx),
|
||||||
|
};
|
||||||
|
|
||||||
|
DEVICE_AND_API_INIT(mcux_adc12_2, DT_NXP_KINETIS_ADC12_ADC_2_LABEL,
|
||||||
|
&mcux_adc12_init, &mcux_adc12_data_2, &mcux_adc12_config_2,
|
||||||
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||||
|
&mcux_adc12_driver_api);
|
||||||
|
|
||||||
|
static void mcux_adc12_config_func_2(struct device *dev)
|
||||||
|
{
|
||||||
|
IRQ_CONNECT(DT_NXP_KINETIS_ADC12_ADC_2_IRQ,
|
||||||
|
DT_NXP_KINETIS_ADC12_ADC_2_IRQ_PRIORITY, mcux_adc12_isr,
|
||||||
|
DEVICE_GET(mcux_adc12_2), 0);
|
||||||
|
|
||||||
|
irq_enable(DT_NXP_KINETIS_ADC12_ADC_2_IRQ);
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_ADC_2 */
|
55
dts/bindings/iio/adc/nxp,kinetis-adc12.yaml
Normal file
55
dts/bindings/iio/adc/nxp,kinetis-adc12.yaml
Normal file
|
@ -0,0 +1,55 @@
|
||||||
|
#
|
||||||
|
# Copyright (c) 2019 Vestas Wind Systems A/S
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
#
|
||||||
|
---
|
||||||
|
title: NXP Kinetis ADC12
|
||||||
|
version: 0.1
|
||||||
|
|
||||||
|
description: >
|
||||||
|
This binding gives a base representation of the NXP Kinetis ADC12
|
||||||
|
|
||||||
|
inherits:
|
||||||
|
!include adc.yaml
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
constraint: "nxp,kinetis-adc12"
|
||||||
|
|
||||||
|
reg:
|
||||||
|
type: array
|
||||||
|
description: mmio register space
|
||||||
|
generation: define
|
||||||
|
category: required
|
||||||
|
|
||||||
|
interrupts:
|
||||||
|
type: array
|
||||||
|
category: required
|
||||||
|
description: required interrupts
|
||||||
|
generation: define
|
||||||
|
|
||||||
|
clk-source:
|
||||||
|
type: int
|
||||||
|
category: required
|
||||||
|
description: converter clock source
|
||||||
|
generation: define
|
||||||
|
|
||||||
|
clk-divider:
|
||||||
|
type: int
|
||||||
|
category: required
|
||||||
|
description: clock divider for the converter
|
||||||
|
generation: define
|
||||||
|
|
||||||
|
alternate-voltage-reference:
|
||||||
|
type: boolean
|
||||||
|
category: optional
|
||||||
|
description: use alternate voltage reference source
|
||||||
|
generation: define
|
||||||
|
|
||||||
|
sample-time:
|
||||||
|
type: int
|
||||||
|
category: required
|
||||||
|
description: sample time in clock cycles
|
||||||
|
generation: define
|
||||||
|
...
|
|
@ -12,6 +12,11 @@ config HAS_MCUX
|
||||||
|
|
||||||
if HAS_MCUX
|
if HAS_MCUX
|
||||||
|
|
||||||
|
config HAS_MCUX_ADC12
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
Set if the 12-bit ADC (ADC12) module is present in the SoC.
|
||||||
|
|
||||||
config HAS_MCUX_ADC16
|
config HAS_MCUX_ADC16
|
||||||
bool
|
bool
|
||||||
help
|
help
|
||||||
|
|
|
@ -11,6 +11,7 @@ zephyr_library_compile_definitions_ifdef(
|
||||||
)
|
)
|
||||||
|
|
||||||
zephyr_sources_ifdef(CONFIG_HAS_MCUX_CACHE fsl_cache.c)
|
zephyr_sources_ifdef(CONFIG_HAS_MCUX_CACHE fsl_cache.c)
|
||||||
|
zephyr_sources_ifdef(CONFIG_ADC_MCUX_ADC12 fsl_adc12.c)
|
||||||
zephyr_sources_ifdef(CONFIG_ADC_MCUX_ADC16 fsl_adc16.c)
|
zephyr_sources_ifdef(CONFIG_ADC_MCUX_ADC16 fsl_adc16.c)
|
||||||
zephyr_sources_ifdef(CONFIG_ETH_MCUX fsl_enet.c)
|
zephyr_sources_ifdef(CONFIG_ETH_MCUX fsl_enet.c)
|
||||||
zephyr_sources_ifdef(CONFIG_I2C_MCUX fsl_i2c.c)
|
zephyr_sources_ifdef(CONFIG_I2C_MCUX fsl_i2c.c)
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue