boards: blues: adds Cygnet

Adds new STM32L433 Feather Board from Blues

Signed-off-by: Alex Bucknall <alex.bucknall@gmail.com>

boards/blues/cygnet/Kconfig.cygnet

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+# Copyright (c) 2025 Blues
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CYGNET
+	select SOC_STM32L433XX

boards/blues/cygnet/Kconfig.defconfig

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+# STM32L433CC Cygnet board configuration
+
+# Copyright (c) 2025 Blues
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_CYGNET
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+endif # BOARD_CYGNET

boards/blues/cygnet/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+# keep first
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(jlink "--device=STM32L433CC" "--speed=4000")
+
+# keep first
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/blues/cygnet/board.yml

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+board:
+  name: cygnet
+  full_name: Cygnet
+  vendor: blues
+  socs:
+    - name: stm32l433xx

boards/blues/cygnet/cygnet.dts

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+/*
+ * Copyright (c) 2025 Blues
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/l4/stm32l433Xc.dtsi>
+#include <st/l4/stm32l433c(b-c)ux-pinctrl.dtsi>
+#include "feather_connector.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Blues Cygnet";
+	compatible = "blues,cygnet";
+
+	chosen {
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		user_led: led_0 {
+			gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>;
+			label = "User LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button: button {
+			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+			label = "User Button";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &user_led;
+		sw0 = &user_button;
+	};
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&pll {
+	div-m = <1>;
+	mul-n = <20>;
+	div-p = <7>;
+	div-q = <2>;
+	div-r = <4>;
+	clocks = <&clk_hsi>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(80)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+};
+
+&lpuart1 {
+	pinctrl-0 = <&lpuart1_tx_pb11 &lpuart1_rx_pb10>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpiob 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	status = "okay";
+};
+
+&timers2 {
+	status = "okay";
+
+	pwm2: pwm {
+		status = "okay";
+		pinctrl-0 = <&tim2_ch1_pa0>;
+		pinctrl-names = "default";
+	};
+};
+
+&can1 {
+	pinctrl-0 = <&can1_rx_pb8 &can1_tx_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
+		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * Reserve the final 16 KiB for file system partition
+		 */
+		storage_partition: partition@3c000 {
+			label = "storage";
+			reg = <0x0003c000 DT_SIZE_K(16)>;
+		};
+	};
+};

boards/blues/cygnet/cygnet.yaml

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+identifier: cygnet
+name: Blues Cygnet
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 64
+flash: 256
+supported:
+  - nvs
+  - can
+  - spi
+  - i2c
+  - pwm
+  - gpio
+  - counter
+  - feather_serial
+  - feather_i2c
+  - feather_spi
+vendor: blues

boards/blues/cygnet/cygnet_defconfig

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+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/blues/cygnet/doc/index.rst

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+.. zephyr:board:: cygnet
+
+Overview
+********
+
+The Blues Cygnet board features an ARM Cortex-M4 based STM32L433CC MCU
+with a wide range of connectivity support and configurations. Here are
+some highlights of the Cygnet board:
+
+- STM32L4 microcontroller in LQFP48 package
+- Adafruit Feather connector
+- User LED
+- User push-button
+- USB Type-C connector
+
+More information about the board can be found at the `Blues Cygnet website`_.
+
+Hardware
+********
+
+The STM32L433CC SoC provides the following hardware IPs:
+
+- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84
+  |micro| A/MHz run mode)
+- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz,
+  100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
+- Clock Sources:
+
+  - 32 kHz crystal oscillator for RTC (LSE)
+  - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
+  - Internal low-power 32 kHz RC ( |plusminus| 5%)
+  - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
+    LSE (better than |plusminus| 0.25 % accuracy)
+  - 2 PLLs for system clock, USB, audio, ADC
+
+- RTC with HW calendar, alarms and calibration
+- 11x timers:
+
+  - 1x 16-bit advanced motor-control
+  - 1x 32-bit and 2x 16-bit general purpose
+  - 2x 16-bit basic
+  - 2x low-power 16-bit timers (available in Stop mode)
+  - 2x watchdogs
+  - SysTick timer
+
+- Up to 21 fast I/Os, most 5 V-tolerant
+- Memories
+
+  - Up to 256 KB single bank Flash, proprietary code readout protection
+  - 64 KB of SRAM including 16 KB with hardware parity check
+
+- Rich analog peripherals (independent supply)
+
+  - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200
+    |micro| A/MSPS
+  - 2x 12-bit DAC output channels, low-power sample and hold
+  - 1x operational amplifiers with built-in PGA
+  - 2x ultra-low-power comparators
+
+- 17x communication interfaces
+
+  - USB 2.0 full-speed crystal less solution with LPM and BCD
+  - 1x SAI (serial audio interface)
+  - 3x I2C FM+(1 Mbit/s), SMBus/PMBus
+  - 4x USARTs (ISO 7816, LIN, IrDA, modem)
+  - 1x LPUART (Stop 2 wake-up)
+  - 3x SPIs (and 1x Quad SPI)
+  - CAN (2.0B Active)
+
+- 14-channel DMA controller
+- True random number generator
+- CRC calculation unit, 96-bit unique ID
+- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell*
+
+More information about STM32L433CC can be found here:
+
+- `STM32L433CC on www.st.com`_
+- `STM32L432 reference manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+.. note:: CAN feature requires a CAN transceiver.
+
+Connections and IOs
+===================
+
+The Cygnet board has 6 GPIO controllers. These controllers are responsible for pin muxing,
+input/output, pull-up, etc.
+
+Available pins
+--------------
+.. image:: img/cygnet-pinout.webp
+   :align: center
+   :alt: Cygnet Pinout
+
+For more details please refer to `Blues Cygnet User Manual`_.
+
+Default Zephyr Peripheral Mapping
+---------------------------------
+
+- LPUART_1_TX : PB11
+- LPUART_1_RX : PB10
+- UART_1_TX : PA9
+- UART_1_RX : PA10
+- I2C_1_SCL : PB6
+- I2C_1_SDA : PB7
+- PWM_2_CH1 : PA0
+- SPI_1: SCK/MISO/MOSI : PA5/PA6/PB5
+
+System Clock
+------------
+
+The Cygnet board System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
+driven by 16MHz high speed internal oscillator.
+
+Serial Port
+-----------
+
+The Cygnet board has 4 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned
+to LPUART1. Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+The Cygnet board requires an ST-LINK embedded debug tool in order to be programmed and debugged.
+
+Applications for the ``cygnet`` board configuration can be built and
+flashed in the usual way (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Flashing
+========
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
+so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
+
+Alternatively, OpenOCD or JLink can also be used to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner openocd
+   $ west flash --runner jlink
+
+Flashing an application to Cygnet
+---------------------------------
+
+Connect the Cygnet to the ST-LINK debugger, then run a serial host program to connect with your Cygnet board.
+
+.. code-block:: console
+
+   $ picocom /dev/ttyACM0 -b 115200
+
+Now build and flash an application. Here is an example for
+:zephyr:code-sample:`hello_world`.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: cygnet
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   $ Hello World! cygnet
+
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: cygnet
+   :maybe-skip-config:
+   :goals: debug
+
+References
+**********
+
+.. target-notes::
+
+.. _Blues Cygnet website:
+   https://www.blues.dev/
+
+.. _Blues Cygnet User Manual:
+   https://dev.blues.io/feather-mcus/cygnet/cygnet-introduction/
+
+.. _STM32L433CC on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32l433cc.html
+
+.. _STM32L432 reference manual:
+   https://www.st.com/resource/en/reference_manual/dm00151940.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html

boards/blues/cygnet/feather_connector.dtsi

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+/*
+ * Copyright (c) 2025 Blues Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	feather_header: connector {
+		compatible = "adafruit-feather-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 0 0>,	/* A0 */
+					<1 0 &gpioa 1 0>,	/* A1 */
+					<2 0 &gpioa 2 0>,	/* A2 */
+					<3 0 &gpioa 3 0>,	/* A3 */
+					<4 0 &gpiob 1 0>,	/* A4 */
+					<5 0 &gpioa 7 0>,	/* A5 */
+					<6 0 &gpioa 5 0>,	/* SCK */
+					<7 0 &gpiob 5 0>,	/* MOSI */
+					<8 0 &gpioa 6 0>,	/* MISO */
+					<9 0 &gpioa 10 0>,	/* RX */
+					<10 0 &gpioa 9 0>,	/* TX */
+					<11 0 &gpiob 1 0>,	/* D4 */
+					<12 0 &gpiob 7 0>,	/* SDA */
+					<13 0 &gpiob 6 0>,	/* SCL */
+					<14 0 &gpiob 8 0>,	/* D5 */
+					<15 0 &gpiob 9 0>,	/* D6 */
+					<16 0 &gpiob 14 0>,	/* D9 */
+					<17 0 &gpiob 13 0>,	/* D10 */
+					<18 0 &gpiob 0 0>,	/* D11 */
+					<19 0 &gpiob 15 0>,	/* D12 */
+					<20 0 &gpiob 4 0>;	/* D13 */
+	};
+};
+
+feather_serial: &usart1 {};
+feather_i2c: &i2c1 {};
+feather_spi: &spi1 {};

boards/blues/cygnet/support/openocd.cfg

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+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+source [find target/stm32l4x.cfg]
+
+reset_config srst_only