esp32: SPIRAM Support
Adds SPIRAM support for ESP32 Configures k_heap for SPIRAM memory range Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
This commit is contained in:
Shubham Kulkarni
Anas Nashif
parent
61a2e8cee3
commit
67d2368398
3 changed files with 182 additions and 2 deletions
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@ -22,4 +22,150 @@ config ESP32_BT_RESERVE_DRAM
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default 0xdb5c if BT
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default 0
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endif # SOC_ESP32
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config ESP_SPIRAM
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bool "Support for external, SPI-connected RAM"
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help
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This enables support for an external SPI RAM chip, connected in
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parallel with the main SPI flash chip.
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menu "SPI RAM config"
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depends on ESP_SPIRAM
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choice SPIRAM_TYPE
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prompt "Type of SPI RAM chip in use"
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default SPIRAM_TYPE_ESPPSRAM16
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config SPIRAM_TYPE_ESPPSRAM16
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bool "ESP-PSRAM16 or APS1604"
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config SPIRAM_TYPE_ESPPSRAM32
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bool "ESP-PSRAM32 or IS25WP032"
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config SPIRAM_TYPE_ESPPSRAM64
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bool "ESP-PSRAM64 or LY68L6400"
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endchoice
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config ESP_SPIRAM_SIZE
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int "Size of SPIRAM part"
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default 2097152 if SPIRAM_TYPE_ESPPSRAM16
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default 4194304 if SPIRAM_TYPE_ESPPSRAM32
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default 8388608 if SPIRAM_TYPE_ESPPSRAM64
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help
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Specify size of SPIRAM part.
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NOTE: If SPIRAM size is greater than 4MB, only
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lower 4MB can be allocated using k_malloc().
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choice SPIRAM_SPEED
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prompt "Set RAM clock speed"
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default SPIRAM_SPEED_40M
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help
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Select the speed for the SPI RAM chip.
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If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
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1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz
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2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz
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3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz
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Note: If the third mode(80Mhz+80Mhz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
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will be occupied by the system. Which SPI host to use can be selected by the config item
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SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
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option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
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(ESPTOOLPY_FLASHFREQ_79M is true)
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config SPIRAM_SPEED_40M
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bool "40MHz clock speed"
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config SPIRAM_SPEED_80M
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depends on ESPTOOLPY_FLASHFREQ_80M
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bool "80MHz clock speed"
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endchoice
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menu "PSRAM clock and cs IO for ESP32-DOWD"
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config D0WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 17
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help
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The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D0WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 16
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-D2WD"
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config D2WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 9
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D2WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-PICO"
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config PICO_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
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For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
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IO.
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For the reference hardware design, please refer to
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https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
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endmenu
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config SPIRAM_CUSTOM_SPIWP_SD3_PIN
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bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
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default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5
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default n
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help
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This setting is only used if the SPI flash pins have been overridden by setting the eFuses
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SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
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When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
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ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
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mode, so a WP pin setting is necessary.
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If this config item is set to N (default), the correct WP pin will be automatically used for any
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Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
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to Y and specify the GPIO number connected to the WP pin.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
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configured in the bootloader.
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config SPIRAM_SPIWP_SD3_PIN
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int "Custom SPI PSRAM WP(SD3) Pin"
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range 0 33
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default 7
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help
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The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
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If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
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value to the GPIO number of the SPIRAM WP pin.
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config SPIRAM
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bool
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default y
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endmenu
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endif # SOC_ESP32
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@ -45,6 +45,9 @@ MEMORY
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drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20
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rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000
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rtc_slow_seg(RW): org = 0x50000000, len = 0x1000
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#if defined(CONFIG_ESP_SPIRAM)
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ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE
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#endif
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
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#endif
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@ -250,6 +253,15 @@ _net_buf_pool_list = _esp_net_buf_pool_list;
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. = ALIGN(4);
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} GROUP_LINK_IN(RAMABLE_REGION)
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#if defined(CONFIG_ESP_SPIRAM)
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.ext_ram.bss (NOLOAD):
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{
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_ext_ram_data_start = ABSOLUTE(.);
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*(.ext_ram.bss*)
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_ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;
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} > ext_ram_seg
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#endif
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))
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{
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_rodata_start = ABSOLUTE(.);
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@ -22,6 +22,9 @@
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#include "soc/cpu.h"
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#include "soc/gpio_periph.h"
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#include "esp_spi_flash.h"
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#include "esp_err.h"
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#include "esp32/spiram.h"
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#include "sys/printk.h"
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extern void z_cstart(void);
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@ -96,7 +99,26 @@ void __attribute__((section(".iram1"))) __start(void)
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*wdt_rtc_protect = 0;
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#endif
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#if CONFIG_SOC_FLASH_ESP32
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#if CONFIG_ESP_SPIRAM
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esp_err_t err = esp_spiram_init();
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if (err != ESP_OK) {
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printk("Failed to Initialize SPIRAM, aborting.\n");
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abort();
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}
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esp_spiram_init_cache();
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if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) {
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printk("SPIRAM size is less than configured size, aborting.\n");
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abort();
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}
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#endif
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/* Scheduler is not started at this point. Hence, guard functions
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* must be initialized after esp_spiram_init_cache which internally
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* uses guard functions. Setting guard functions before SPIRAM
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* cache initialization will result in a crash.
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*/
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#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM
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spi_flash_guard_set(&g_flash_guard_default_ops);
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#endif
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/* Start Zephyr */
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