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tests: drivers: stm32 clock control testing on stm32wb55

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target is stm32wb55 with clearing clock config
target is stm32wb55 with pll 48MHz from hsi clock config
target is stm32wb55 with pll 48MHz from msi clock config
target is stm32wb55 with pll 64Hz from hse clock config
target is stm32wb55 with hse, msi, hsi clock config (no pll)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-03-01 16:45:20 +01:00 • committed by Maureen Helm
commit 676ddd72a9
6 changed files with 193 additions and 0 deletions
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20
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/hse_32.overlay Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
clock-frequency = <DT_FREQ_M(32)>; /* 32MHz oscillator */
status = "okay";
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(32)>;
};

53
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wb_clear_clocks.overlay Normal file
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@ -0,0 +1,53 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32wb.dtsi
*/
&clk_hse {
status = "disabled";
/delete-property/ hse-bypass;
/delete-property/ clock-frequency;
};
&clk_hsi {
status = "disabled";
/delete-property/ hsi-div;
};
&clk_lse {
status = "disabled";
};
&clk_lsi1 {
status = "disabled";
};
&clk_lsi2 {
status = "disabled";
};
&clk_msi {
status = "disabled";
/delete-property/ msi-range;
};
&pll {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
};

34
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wb_pll_48_hsi_16.overlay Normal file
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@ -0,0 +1,34 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
* It applies to the stm32wb
*/
&clk_hsi {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <9>;
div-p = <2>;
div-q = <2>;
div-r = <3>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
cpu1-prescaler = <1>;
cpu2-prescaler = <2>;
ahb4-prescaler = <2>;
};

34
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wb_pll_48_msi_4.overlay Normal file
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@ -0,0 +1,34 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after wb_clear_clocks.overlay file.
* It applies to the stm32wb where the msi is 4MHz
*/
&clk_msi {
status = "okay";
msi-range = <6>; /* default value */
};
&pll {
div-m = <1>;
mul-n = <24>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_msi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
cpu1-prescaler = <1>;
cpu2-prescaler = <2>;
ahb4-prescaler = <2>;
};

34
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wb_pll_64_hse_32.overlay Normal file
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@ -0,0 +1,34 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
* It applies to the stm32wb
*/
&clk_hse {
clock-frequency = <DT_FREQ_M(32)>; /* X1 32MHz oscillator */
status = "okay";
};
&pll {
div-m = <2>;
mul-n = <8>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(64)>;
cpu1-prescaler = <1>;
cpu2-prescaler = <2>;
ahb4-prescaler = <2>;
};

18
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
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@ -40,3 +40,21 @@ tests:
drivers.stm32_clock_configuration.common.sysclksrc_48_msi: drivers.stm32_clock_configuration.common.sysclksrc_48_msi:
extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/msi_range11.overlay" extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/msi_range11.overlay"
platform_allow: nucleo_wl55jc platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common.sysclksrc_wb_48_msi:
extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/msi_range11.overlay"
platform_allow: nucleo_wb55rg
drivers.stm32_clock_configuration.common.sysclksrc_wb_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_wb55rg
drivers.stm32_clock_configuration.common.sysclksrc_wb_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/hse_32.overlay"
platform_allow: nucleo_wb55rg
drivers.stm32_clock_configuration.common.sysclksrc_wb_pll_48_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/wb_pll_48_hsi_16.overlay"
platform_allow: nucleo_wb55rg
drivers.stm32_clock_configuration.common.sysclksrc_wb_pll_64_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/wb_pll_64_hse_32.overlay"
platform_allow: nucleo_wb55rg
drivers.stm32_clock_configuration.common.sysclksrc_wb_pll_48_msi_4:
extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/wb_pll_48_msi_4.overlay"
platform_allow: nucleo_wb55rg