arch/x86: remove support for IAMCU ABI
This ABI is no longer required by any targets and is deprecated. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse
Anas Nashif
parent
37929b3428
commit
6767563f94
25 changed files with 20 additions and 273 deletions
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@ -114,16 +114,6 @@ config X86_BOUNDS_CHECK_BYPASS_MITIGATION
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menu "Processor Capabilities"
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config X86_IAMCU
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bool "IAMCU calling convention"
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help
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The IAMCU calling convention changes the X86 C calling convention to
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pass some arguments via registers allowing for code size and performance
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improvements. Great care needs to be taken if you have assembly code
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that will be called from C or C code called from assembly code, the
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assembly code will need to be updated to conform to the new calling
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convention. If in doubt say N
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config X86_MMU
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bool "Enable Memory Management Unit"
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select MEMORY_PROTECTION
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@ -3,7 +3,7 @@
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if (CMAKE_C_COMPILER_ID STREQUAL "Clang")
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# We rely on GAS for assembling, so don't use the integrated assembler
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zephyr_compile_options_ifndef(CONFIG_X86_IAMCU $<$<COMPILE_LANGUAGE:ASM>:-no-integrated-as>)
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zephyr_compile_options($<$<COMPILE_LANGUAGE:ASM>:-no-integrated-as>)
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elseif(CMAKE_C_COMPILER_ID STREQUAL "GNU")
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zephyr_compile_options($<$<COMPILE_LANGUAGE:ASM>:-Wa,--divide>)
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endif()
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@ -161,16 +161,9 @@ SECTION_FUNC(TEXT, _exception_enter)
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sti
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allDone:
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#if CONFIG_X86_IAMCU
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movl %esp, %eax /* z_arch_esf_t * parameter */
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#else
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pushl %esp /* push z_arch_esf_t * parameter */
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#endif
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INDIRECT_CALL(%ecx) /* call exception handler */
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#ifndef CONFIG_X86_IAMCU
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addl $0x4, %esp
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#endif
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#if defined(CONFIG_LAZY_FP_SHARING)
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@ -105,12 +105,8 @@ static void unwind_stack(u32_t base_ptr, u16_t cs)
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if (frame->ret_addr == 0U) {
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break;
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}
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#ifdef CONFIG_X86_IAMCU
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z_fatal_print(" 0x%08x", frame->ret_addr);
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#else
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z_fatal_print(" 0x%08x (0x%x)", frame->ret_addr,
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frame->args);
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#endif
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base_ptr = frame->next;
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}
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}
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@ -178,12 +178,8 @@ SECTION_FUNC(TEXT, _interrupt_enter)
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alreadyOnIntStack:
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#ifndef CONFIG_X86_IAMCU
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/* EAX has the interrupt handler argument, needs to go on
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* stack for sys V calling convention
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*/
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push %eax
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#endif
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push %eax /* interrupt handler argument */
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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/* Save the eax and edx registers before reading the time stamp
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* once done pop the values
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@ -202,10 +198,8 @@ alreadyOnIntStack:
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#endif
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/* Now call the interrupt handler */
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INDIRECT_CALL(%edx)
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#ifndef CONFIG_X86_IAMCU
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/* Discard ISR argument */
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addl $0x4, %esp
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#endif
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#ifdef CONFIG_NESTED_INTERRUPTS
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cli /* disable interrupts again */
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#endif
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@ -255,16 +249,9 @@ alreadyOnIntStack:
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call z_check_stack_sentinel
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#endif
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pushfl /* push KERNEL_LOCK_KEY argument */
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#ifdef CONFIG_X86_IAMCU
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/* IAMCU first argument goes into a register, not the stack.
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*/
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popl %eax
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#endif
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call __swap
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#ifndef CONFIG_X86_IAMCU
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addl $4, %esp /* pop KERNEL_LOCK_KEY argument */
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#endif
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/*
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* The interrupted thread has now been scheduled,
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* as the result of a _later_ invocation of __swap().
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@ -331,12 +318,7 @@ handle_idle:
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pushl %eax
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pushl %edx
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/* Populate 'ticks' argument to z_sys_power_save_idle_exit */
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#ifdef CONFIG_X86_IAMCU
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movl _kernel_offset_to_idle(%ecx), %eax
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#else
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/* SYS V calling convention */
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push _kernel_offset_to_idle(%ecx)
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#endif
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/* Zero out _kernel.idle */
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movl $0, _kernel_offset_to_idle(%ecx)
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@ -348,10 +330,8 @@ handle_idle:
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*/
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call z_sys_power_save_idle_exit
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#ifndef CONFIG_X86_IAMCU
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/* SYS V: discard 'ticks' argument passed on the stack */
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/* discard 'ticks' argument passed on the stack */
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add $0x4, %esp
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#endif
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popl %edx
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popl %eax
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jmp alreadyOnIntStack
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@ -409,11 +389,7 @@ SECTION_FUNC(TEXT, z_SpuriousIntHandler)
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leal 44(%esp), %ecx /* Calculate ESP before exception occurred */
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pushl %ecx /* Save calculated ESP */
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#ifndef CONFIG_X86_IAMCU
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pushl %esp /* push cur stack pointer: pEsf arg */
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#else
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mov %esp, %eax
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#endif
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/* re-enable interrupts */
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sti
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@ -97,13 +97,6 @@ SECTION_FUNC(TEXT, __swap)
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mov %edx,__start_swap_time+4
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pop %edx
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pop %eax
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#endif
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#ifdef CONFIG_X86_IAMCU
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/* save EFLAGS on stack right before return address, just as SYSV would
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* have done
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*/
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pushl 0(%esp)
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movl %eax, 4(%esp)
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#endif
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/*
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* Push all non-volatile registers onto the stack; do not copy
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@ -150,17 +143,10 @@ SECTION_FUNC(TEXT, __swap)
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*/
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#if defined(CONFIG_X86_USERSPACE) && !defined(CONFIG_X86_KPTI)
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#ifdef CONFIG_X86_IAMCU
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push %eax
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#else
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push %eax
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#endif
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call z_x86_swap_update_page_tables
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#ifdef CONFIG_X86_IAMCU
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pop %eax
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#else
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pop %eax
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#endif
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/* Page tables updated. All memory access after this point needs to be
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* to memory that has the same mappings and access attributes wrt
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* supervisor mode!
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@ -379,14 +365,6 @@ CROHandlingDone:
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pushl 4(%esp)
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popfl
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#if CONFIG_X86_IAMCU
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/* Remember that eflags we stuck into the stack before the return
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* address? need to get it out of there since the calling convention
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* will not do that for us.
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*/
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popl %edx
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movl %edx, (%esp)
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#endif
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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/* Save the eax and edx registers before reading the time stamp
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@ -409,17 +387,13 @@ time_read_not_needed:
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*
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* This function adjusts the initial stack frame created by z_new_thread() such
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* that the GDB stack frame unwinders recognize it as the outermost frame in
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* the thread's stack. For targets that use the IAMCU calling convention, the
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* first three arguments are popped into eax, edx, and ecx. The function then
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* jumps to z_thread_entry().
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* the thread's stack.
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*
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* GDB normally stops unwinding a stack when it detects that it has
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* reached a function called main(). Kernel threads, however, do not have
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* a main() function, and there does not appear to be a simple way of stopping
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* the unwinding of the stack.
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*
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* SYS V Systems:
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*
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* Given the initial thread created by z_new_thread(), GDB expects to find a
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* return address on the stack immediately above the thread entry routine
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* z_thread_entry, in the location occupied by the initial EFLAGS.
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@ -436,15 +410,6 @@ time_read_not_needed:
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* first time that the new thread is swapped in, and it jumps to
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* z_thread_entry after it has done its work.
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*
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* IAMCU Systems:
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*
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* There is no EFLAGS on the stack when we get here. z_thread_entry() takes
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* four arguments, and we need to pop off the first three into the
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* appropriate registers. Instead of using the 'call' instruction, we push
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* a NULL return address onto the stack and jump into z_thread_entry,
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* ensuring the stack won't be unwound further. Placing some kind of return
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* address on the stack is mandatory so this isn't conditionally compiled.
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*
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* __________________
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* | param3 | <------ Top of the stack
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* |__________________|
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@ -452,10 +417,10 @@ time_read_not_needed:
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* |__________________| |
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* | param1 | V
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* |__________________|
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* | pEntry | <---- ESP when invoked by z_swap() on IAMCU
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* | pEntry |
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* |__________________|
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* | initial EFLAGS | <---- ESP when invoked by z_swap() on Sys V
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* |__________________| (Zeroed by this routine on Sys V)
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* | initial EFLAGS | <---- ESP when invoked by z_swap()
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* |__________________| (Zeroed by this routine)
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*
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* The address of the thread entry function needs to be in %edi when this is
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* invoked. It will either be z_thread_entry, or if userspace is enabled,
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@ -465,15 +430,6 @@ time_read_not_needed:
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*/
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SECTION_FUNC(TEXT, z_x86_thread_entry_wrapper)
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#ifdef CONFIG_X86_IAMCU
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/* IAMCU calling convention has first 3 arguments supplied in
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* registers not the stack
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*/
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pop %eax
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pop %edx
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pop %ecx
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push $0 /* Null return address */
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#endif
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movl $0, (%esp)
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INDIRECT_JMP(%edi)
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#endif /* _THREAD_WRAPPER_REQUIRED */
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@ -218,11 +218,9 @@ _id_ok:
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push %ebp /* arg6 */
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push %edi /* arg5 */
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push %ebx /* arg4 */
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#ifndef CONFIG_X86_IAMCU
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push %ecx /* arg3 */
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push %edx /* arg2 */
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push %eax /* arg1 */
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#endif
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/* from the call ID in ESI, load EBX with the actual function pointer
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* to call by looking it up in the system call dispatch table
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@ -236,20 +234,13 @@ _id_ok:
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/* EAX now contains return value. Pop or xor everything else to prevent
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* information leak from kernel mode.
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*/
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#ifndef CONFIG_X86_IAMCU
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pop %edx /* old arg1 value, discard it */
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pop %edx
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pop %ecx
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#endif
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pop %ebx
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pop %edi
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#ifndef CONFIG_X86_IAMCU
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/* Discard ssf and arg6 */
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add $8, %esp
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#else
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pop %ecx /* Clean ECX and get arg6 off the stack */
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pop %edx /* Clean EDX and get ssf off the stack */
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#endif
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KPTI_IRET_USER
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_bad_syscall:
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@ -314,11 +305,9 @@ SECTION_FUNC(TEXT, z_x86_userspace_enter)
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pop %esi /* Discard return address on stack */
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/* Fetch parameters on the stack */
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#ifndef CONFIG_X86_IAMCU
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pop %eax /* user_entry */
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pop %edx /* p1 */
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pop %ecx /* p2 */
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#endif
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pop %esi /* p3 */
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pop %ebx /* stack_end (high address) */
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pop %edi /* stack_start (low address) */
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@ -377,11 +366,9 @@ SECTION_FUNC(TEXT, z_x86_userspace_enter)
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/* Push arguments to z_thread_entry() */
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push %esi /* p3 */
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#ifndef CONFIG_X86_IAMCU
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push %ecx /* p2 */
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push %edx /* p1 */
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push %eax /* user_entry */
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#endif
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/* NULL return address */
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push $0
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@ -9,23 +9,11 @@ else()
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zephyr_compile_definitions(PERF_OPT)
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endif()
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if(CONFIG_X86_IAMCU)
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set_property(GLOBAL APPEND PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES -D__IAMCU)
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-iamcu")
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_ARCH "iamcu:intel")
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else()
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_ARCH "i386")
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-i386")
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endif()
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_ARCH "i386")
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-i386")
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if(CMAKE_C_COMPILER_ID STREQUAL "Clang")
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if(CONFIG_X86_IAMCU)
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zephyr_compile_options(-miamcu)
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else()
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zephyr_compile_options(-Qunused-arguments)
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endif()
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zephyr_cc_option(
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-m32
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@ -42,11 +42,10 @@
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/* Some configurations require that the stack/registers be adjusted before
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* z_thread_entry. See discussion in swap.S for z_x86_thread_entry_wrapper()
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*/
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#if defined(CONFIG_X86_IAMCU) || defined(CONFIG_DEBUG_INFO)
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#if defined(CONFIG_DEBUG_INFO)
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#define _THREAD_WRAPPER_REQUIRED
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#endif
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/* increase to 16 bytes (or more?) to support SSE/SSE2 instructions? */
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#define STACK_ALIGN_SIZE 4
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@ -7,5 +7,5 @@
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config BOARD_ACRN
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bool "ACRN User OS"
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depends on SOC_IA32
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select CPU_HAS_FPU if !X86_IAMCU
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select CPU_HAS_FPU
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select SET_GDT
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@ -13,11 +13,3 @@ config BOARD_QEMU_X86
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select CPU_HAS_FPU
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select HAS_COVERAGE_SUPPORT
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select XIP
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config BOARD_QEMU_X86_IAMCU
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bool "QEMU x86 (IAMCU ABI)"
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depends on SOC_IA32
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select QEMU_TARGET
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select HAS_DTS_ETHERNET
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select HAS_COVERAGE_SUPPORT
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select XIP
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@ -17,21 +17,3 @@ config FLASH_SIMULATOR
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endif
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endif # BOARD_QEMU_X86
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if BOARD_QEMU_X86_IAMCU
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config BUILD_OUTPUT_BIN
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default n
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config BOARD
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default "qemu_x86_iamcu"
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# Enabled here because IAMCU targets run on some Quark CPUs that are immune to
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# these attacks, and the compiler doesn't even recognize instructions like
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# 'lfence'
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# We set this here because the QEMU targets derive from the generic IA32 SOC
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# definition and not a specific CPU; this is normally set at the SOC level.
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config X86_NO_SPECULATIVE_VULNERABILITIES
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default y
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endif # BOARD_QEMU_X86_IAMCU
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@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: Apache-2.0 */
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#include "qemu_x86.dts"
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@ -1,11 +0,0 @@
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identifier: qemu_x86_iamcu
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name: QEMU Emulation for X86 (IAMCU)
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type: qemu
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arch: x86
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toolchain:
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- zephyr
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- xtools
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testing:
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ignore_tags:
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- net
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- bluetooth
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@ -1,19 +0,0 @@
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_X86=y
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CONFIG_SOC_IA32=y
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CONFIG_BOARD_QEMU_X86_IAMCU=y
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CONFIG_CPU_MINUTEIA=y
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CONFIG_HPET_TIMER=y
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CONFIG_HPET_TIMER_IRQ=2
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CONFIG_PIC_DISABLE=y
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CONFIG_LOAPIC=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_NS16550=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
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CONFIG_X86_IAMCU=y
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CONFIG_X86_MMU=y
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CONFIG_X86_MMU_PAGE_POOL_PAGES=15
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CONFIG_DEBUG_INFO=y
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@ -43,13 +43,6 @@ if (CONFIG_X86)
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OUTPUT_STRIP_TRAILING_WHITESPACE
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)
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assert_exists(LIBGCC_FILE_NAME)
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# While most x86_64 Linux distributions implement "multilib" and have
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# 32 bits libraries off the shelf, things like
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# "/usr/lib/gcc/x86_64-linux-gnu/7/IAMCU/libgcc.a" are unheard of.
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# So this fails CONFIG_X86_IAMCU=y with a "cannot find -lgcc" error which
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# is clearer than "undefined reference to __udivdi3, etc."
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LIST(APPEND TOOLCHAIN_LIBS gcc)
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endif()
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set(NOSTDINC "")
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@ -233,15 +233,6 @@ elseif(QEMU_NET_STACK)
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endif()
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endif(QEMU_PIPE_STACK)
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if(CONFIG_X86_IAMCU)
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||||
list(APPEND PRE_QEMU_COMMANDS
|
||||
COMMAND
|
||||
${PYTHON_EXECUTABLE}
|
||||
${ZEPHYR_BASE}/scripts/qemu-machine-hack.py
|
||||
$<TARGET_FILE:${logical_target_for_zephyr_elf}>
|
||||
)
|
||||
endif()
|
||||
|
||||
if(CONFIG_X86_64)
|
||||
set(QEMU_KERNEL_FILE "${CMAKE_BINARY_DIR}/zephyr-qemu.elf")
|
||||
endif()
|
||||
|
|
|
|||
|
|
@ -1,12 +1,5 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Determine if we have an IAMCU toolchain or not.
|
||||
if(CONFIG_X86_IAMCU)
|
||||
set(CROSS_COMPILE_TARGET_x86 i586-zephyr-elfiamcu)
|
||||
else()
|
||||
set(CROSS_COMPILE_TARGET_x86 i586-zephyr-elf)
|
||||
endif()
|
||||
|
||||
set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi)
|
||||
set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_riscv riscv32-zephyr-elf)
|
||||
|
|
@ -14,6 +7,7 @@ set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf)
|
|||
set(CROSS_COMPILE_TARGET_xtensa xtensa-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_arc arc-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_x86_64 x86_64-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_x86 i586-zephyr-elf)
|
||||
|
||||
set(CROSS_COMPILE_TARGET ${CROSS_COMPILE_TARGET_${ARCH}})
|
||||
set(SYSROOT_TARGET ${CROSS_COMPILE_TARGET})
|
||||
|
|
|
|||
|
|
@ -1,12 +1,5 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Determine if we have an IAMCU toolchain or not.
|
||||
if(CONFIG_X86_IAMCU)
|
||||
set(CROSS_COMPILE_TARGET_x86 i586-zephyr-elfiamcu)
|
||||
else()
|
||||
set(CROSS_COMPILE_TARGET_x86 i586-zephyr-elf)
|
||||
endif()
|
||||
|
||||
set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi)
|
||||
set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_riscv riscv64-zephyr-elf)
|
||||
|
|
@ -14,6 +7,7 @@ set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf)
|
|||
set(CROSS_COMPILE_TARGET_xtensa xtensa-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_arc arc-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_x86_64 x86_64-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_x86 i586-zephyr-elf)
|
||||
|
||||
set(CROSS_COMPILE_TARGET ${CROSS_COMPILE_TARGET_${ARCH}})
|
||||
set(SYSROOT_TARGET ${CROSS_COMPILE_TARGET})
|
||||
|
|
|
|||
|
|
@ -169,8 +169,6 @@ following target architectures:
|
|||
|
||||
* :abbr:`X86 (Intel Architecture 32 bits)`
|
||||
|
||||
* :abbr:`X86 IAMCU ABI (Intel Architecture 32 bits IAMCU ABI)`
|
||||
|
||||
* :abbr:`Arm (Advanced RISC Machine)`
|
||||
|
||||
* :abbr:`ARC (Argonaut RISC Core)`
|
||||
|
|
|
|||
|
|
@ -10,7 +10,6 @@ Interface)` that is not currently supported.
|
|||
The following are examples of ISAs and ABIs that Zephyr supports:
|
||||
|
||||
* x86_32 ISA with System V ABI
|
||||
* x86_32 ISA with IAMCU ABI
|
||||
* ARMv7-M ISA with Thumb2 instruction set and ARM Embedded ABI (aeabi)
|
||||
* ARCv2 ISA
|
||||
|
||||
|
|
|
|||
|
|
@ -32,8 +32,6 @@ extern "C" {
|
|||
/* Syscall invocation macros. x86-specific machine constraints used to ensure
|
||||
* args land in the proper registers, see implementation of
|
||||
* z_x86_syscall_entry_stub in userspace.S
|
||||
*
|
||||
* the entry stub clobbers EDX and ECX on IAMCU systems
|
||||
*/
|
||||
|
||||
static inline u32_t z_arch_syscall_invoke6(u32_t arg1, u32_t arg2, u32_t arg3,
|
||||
|
|
@ -47,9 +45,6 @@ static inline u32_t z_arch_syscall_invoke6(u32_t arg1, u32_t arg2, u32_t arg3,
|
|||
"int $0x80\n\t"
|
||||
"pop %%ebp\n\t"
|
||||
: "=a" (ret)
|
||||
#ifdef CONFIG_X86_IAMCU
|
||||
, "=d" (arg2), "=c" (arg3)
|
||||
#endif
|
||||
: "S" (call_id), "a" (arg1), "d" (arg2),
|
||||
"c" (arg3), "b" (arg4), "D" (arg5),
|
||||
[arg6] "m" (arg6)
|
||||
|
|
@ -64,9 +59,6 @@ static inline u32_t z_arch_syscall_invoke5(u32_t arg1, u32_t arg2, u32_t arg3,
|
|||
|
||||
__asm__ volatile("int $0x80"
|
||||
: "=a" (ret)
|
||||
#ifdef CONFIG_X86_IAMCU
|
||||
, "=d" (arg2), "=c" (arg3)
|
||||
#endif
|
||||
: "S" (call_id), "a" (arg1), "d" (arg2),
|
||||
"c" (arg3), "b" (arg4), "D" (arg5)
|
||||
: "memory");
|
||||
|
|
@ -80,9 +72,6 @@ static inline u32_t z_arch_syscall_invoke4(u32_t arg1, u32_t arg2, u32_t arg3,
|
|||
|
||||
__asm__ volatile("int $0x80"
|
||||
: "=a" (ret)
|
||||
#ifdef CONFIG_X86_IAMCU
|
||||
, "=d" (arg2), "=c" (arg3)
|
||||
#endif
|
||||
: "S" (call_id), "a" (arg1), "d" (arg2), "c" (arg3),
|
||||
"b" (arg4)
|
||||
: "memory");
|
||||
|
|
@ -96,9 +85,6 @@ static inline u32_t z_arch_syscall_invoke3(u32_t arg1, u32_t arg2, u32_t arg3,
|
|||
|
||||
__asm__ volatile("int $0x80"
|
||||
: "=a" (ret)
|
||||
#ifdef CONFIG_X86_IAMCU
|
||||
, "=d" (arg2), "=c" (arg3)
|
||||
#endif
|
||||
: "S" (call_id), "a" (arg1), "d" (arg2), "c" (arg3)
|
||||
: "memory");
|
||||
return ret;
|
||||
|
|
@ -110,14 +96,8 @@ static inline u32_t z_arch_syscall_invoke2(u32_t arg1, u32_t arg2, u32_t call_id
|
|||
|
||||
__asm__ volatile("int $0x80"
|
||||
: "=a" (ret)
|
||||
#ifdef CONFIG_X86_IAMCU
|
||||
, "=d" (arg2)
|
||||
#endif
|
||||
: "S" (call_id), "a" (arg1), "d" (arg2)
|
||||
: "memory"
|
||||
#ifdef CONFIG_X86_IAMCU
|
||||
, "ecx"
|
||||
#endif
|
||||
);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -130,9 +110,6 @@ static inline u32_t z_arch_syscall_invoke1(u32_t arg1, u32_t call_id)
|
|||
: "=a" (ret)
|
||||
: "S" (call_id), "a" (arg1)
|
||||
: "memory"
|
||||
#ifdef CONFIG_X86_IAMCU
|
||||
, "edx", "ecx"
|
||||
#endif
|
||||
);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -145,9 +122,6 @@ static inline u32_t z_arch_syscall_invoke0(u32_t call_id)
|
|||
: "=a" (ret)
|
||||
: "S" (call_id)
|
||||
: "memory"
|
||||
#ifdef CONFIG_X86_IAMCU
|
||||
, "edx", "ecx"
|
||||
#endif
|
||||
);
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -25,13 +25,8 @@
|
|||
#elif defined(CONFIG_ARC)
|
||||
OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")
|
||||
#elif defined(CONFIG_X86)
|
||||
#if defined(__IAMCU)
|
||||
OUTPUT_FORMAT("elf32-iamcu")
|
||||
OUTPUT_ARCH("iamcu:intel")
|
||||
#else
|
||||
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
|
||||
OUTPUT_ARCH("i386")
|
||||
#endif
|
||||
#elif defined(CONFIG_NIOS2)
|
||||
OUTPUT_FORMAT("elf32-littlenios2", "elf32-bignios2", "elf32-littlenios2")
|
||||
#elif defined(CONFIG_RISCV)
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
import sys
|
||||
|
||||
# For some baffling reason IAMCU sets the instruction set architecture
|
||||
# in the ELF header to 0x06 instead of 0x03 even though it is just
|
||||
# 386 code. This gives QEMU fits. Hack it!
|
||||
fd = open(sys.argv[1], "r+b")
|
||||
fd.seek(0x12)
|
||||
# Write 0x03 which is EM_386 to e_machine
|
||||
fd.write(b'\x03')
|
||||
fd.close()
|
||||
|
|
@ -5,8 +5,4 @@ zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
|
|||
|
||||
zephyr_cc_option(-march=pentium)
|
||||
|
||||
if(CONFIG_X86_IAMCU)
|
||||
zephyr_cc_option(-msoft-float)
|
||||
endif()
|
||||
|
||||
zephyr_library_sources(soc.c)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue