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include/drivers/clock_control: stm32: Bits for H7 dts clock config

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Add required macros to introduce dts based clock_control driver
configuration on stm32h7 devices.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-04-29 14:38:57 +02:00 • committed by Carles Cufí
commit 675990c5e1
1 changed files with 51 additions and 1 deletions
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52
include/drivers/clock_control/stm32_clock_control.h
View file

@ -75,13 +75,31 @@
#define STM32_CPU2_PRESCALER CONFIG_CLOCK_STM32_CPU2_PRESCALER
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32h7_rcc, okay) && \
DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks)
#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
#define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
#else
#define STM32_D1CPRE CONFIG_CLOCK_STM32_D1CPRE
#define STM32_HPRE CONFIG_CLOCK_STM32_HPRE
#define STM32_D2PPRE1 CONFIG_CLOCK_STM32_D2PPRE1
#define STM32_D2PPRE2 CONFIG_CLOCK_STM32_D2PPRE2
#define STM32_D1PPRE CONFIG_CLOCK_STM32_D1PPRE
#define STM32_D3PPRE CONFIG_CLOCK_STM32_D3PPRE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay)
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay)
#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
#define STM32_PLL_P_DIVISOR DT_PROP(DT_NODELABEL(pll), div_p)
@ -95,6 +113,28 @@
#define STM32_PLL_R_DIVISOR CONFIG_CLOCK_STM32_PLL_R_DIVISOR
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay)
#define STM32_PLL3_ENABLE 1
#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
#define STM32_PLL3_P_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
#define STM32_PLL3_P_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p)
#define STM32_PLL3_Q_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
#define STM32_PLL3_Q_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_q)
#define STM32_PLL3_R_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
#define STM32_PLL3_R_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_r)
#else
#define STM32_PLL3_ENABLE CONFIG_CLOCK_STM32_PLL3_ENABLE
#define STM32_PLL3_M_DIVISOR CONFIG_CLOCK_STM32_PLL3_M_DIVISOR
#define STM32_PLL3_N_MULTIPLIER CONFIG_CLOCK_STM32_PLL3_N_MULTIPLIER
#define STM32_PLL3_P_ENABLE CONFIG_CLOCK_STM32_PLL3_P_ENABLE
#define STM32_PLL3_P_DIVISOR CONFIG_CLOCK_STM32_PLL3_P_DIVISOR
#define STM32_PLL3_Q_ENABLE CONFIG_CLOCK_STM32_PLL3_Q_ENABLE
#define STM32_PLL3_Q_DIVISOR CONFIG_CLOCK_STM32_PLL3_Q_DIVISOR
#define STM32_PLL3_R_ENABLE CONFIG_CLOCK_STM32_PLL3_R_ENABLE
#define STM32_PLL3_R_DIVISOR CONFIG_CLOCK_STM32_PLL3_R_DIVISOR
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtre)
#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
@ -118,6 +158,7 @@
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32_rcc, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32f0_rcc, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32h7_rcc, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wb_rcc, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wl_rcc, okay)) && \
DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks)
@ -126,11 +167,13 @@
#define STM32_SYSCLK_SRC_HSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
#define STM32_SYSCLK_SRC_HSE DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
#define STM32_SYSCLK_SRC_MSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
#define STM32_SYSCLK_SRC_CSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
#else
#define STM32_SYSCLK_SRC_PLL CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
#define STM32_SYSCLK_SRC_HSI CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI
#define STM32_SYSCLK_SRC_HSE CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE
#define STM32_SYSCLK_SRC_MSI CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI
#define STM32_SYSCLK_SRC_CSI CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI
#endif
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
@ -141,6 +184,7 @@
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay)) && \
@ -176,6 +220,12 @@
#define STM32_MSI_PLL_MODE CONFIG_CLOCK_STM32_MSI_PLL_MODE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay)
#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
#else
#define STM32_HSI_DIVISOR CONFIG_CLOCK_STM32_HSI_DIVISOR
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
#else