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drivers: gpio: Align the style all over the drivers

Browse source 
Fixing:
- indentation
- 80 chars limit
- { } mandatory on relevant statements
- using BIT() macro relevantly

Change-Id: Ib84eb29530b175c8a533c1b361aea2632f0d7917
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2016-03-23 10:53:04 +01:00 • committed by Gerrit Code Review
commit 67196bc0c3
10 changed files with 177 additions and 196 deletions
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20
drivers/gpio/gpio_atmel_sam3.c
View file

@ -117,7 +117,7 @@ static int gpio_sam3_config(struct device *dev, int access_op,
{
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
_config(dev, (1 << pin), flags);
_config(dev, BIT(pin), flags);
break;
case GPIO_ACCESS_BY_PORT:
_config(dev, (0xFFFFFFFF), flags);
@ -148,10 +148,10 @@ static int gpio_sam3_write(struct device *dev, int access_op,
case GPIO_ACCESS_BY_PIN:
if (value) {
/* set the pin */
cfg->port->sodr = (1 << pin);
cfg->port->sodr = BIT(pin);
} else {
/* clear the pin */
cfg->port->codr = (1 << pin);
cfg->port->codr = BIT(pin);
}
break;
case GPIO_ACCESS_BY_PORT:
@ -221,7 +221,7 @@ static void gpio_sam3_isr(void *arg)
int_stat &= cfg->enabled_cb;
for (bit = 0; bit < 32; bit++) {
if (int_stat & (1 << bit)) {
if (int_stat & BIT(bit)) {
cfg->cb(dev, bit);
}
}
@ -246,7 +246,7 @@ static int gpio_sam3_enable_callback(struct device *dev,
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
mask = (1 << pin);
mask = BIT(pin);
break;
case GPIO_ACCESS_BY_PORT:
mask = 0xFFFFFFFF;
@ -269,7 +269,7 @@ static int gpio_sam3_disable_callback(struct device *dev,
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
mask = (1 << pin);
mask = BIT(pin);
break;
case GPIO_ACCESS_BY_PORT:
mask = 0xFFFFFFFF;
@ -343,7 +343,7 @@ DEVICE_INIT(gpio_sam3_a, CONFIG_GPIO_ATMEL_SAM3_PORTA_DEV_NAME,
void gpio_sam3_config_a(struct device *dev)
{
/* Enable clock for PIO controller */
__PMC->pcer0 = (1 << PID_PIOA);
__PMC->pcer0 = BIT(PID_PIOA);
IRQ_CONNECT(IRQ_PIOA, CONFIG_GPIO_ATMEL_SAM3_PORTA_IRQ_PRI,
gpio_sam3_isr, DEVICE_GET(gpio_sam3_a), 0);
@ -368,7 +368,7 @@ DEVICE_INIT(gpio_sam3_b, CONFIG_GPIO_ATMEL_SAM3_PORTB_DEV_NAME,
void gpio_sam3_config_b(struct device *dev)
{
/* Enable clock for PIO controller */
__PMC->pcer0 = (1 << PID_PIOB);
__PMC->pcer0 = BIT(PID_PIOB);
IRQ_CONNECT(IRQ_PIOB, CONFIG_GPIO_ATMEL_SAM3_PORTB_IRQ_PRI,
gpio_sam3_isr, DEVICE_GET(gpio_sam3_b), 0);
@ -393,7 +393,7 @@ DEVICE_INIT(gpio_sam3_c, CONFIG_GPIO_ATMEL_SAM3_PORTC_DEV_NAME,
void gpio_sam3_config_c(struct device *dev)
{
/* Enable clock for PIO controller */
__PMC->pcer0 = (1 << PID_PIOC);
__PMC->pcer0 = BIT(PID_PIOC);
IRQ_CONNECT(IRQ_PIOC, CONFIG_GPIO_ATMEL_SAM3_PORTC_IRQ_PRI,
gpio_sam3_isr, DEVICE_GET(gpio_sam3_c), 0);
@ -418,7 +418,7 @@ DEVICE_INIT(gpio_sam3_d, CONFIG_GPIO_ATMEL_SAM3_PORTD_DEV_NAME,
void gpio_sam3_config_d(struct device *dev)
{
/* Enable clock for PIO controller */
__PMC->pcer0 = (1 << PID_PIOD);
__PMC->pcer0 = BIT(PID_PIOD);
IRQ_CONNECT(IRQ_PIOD, CONFIG_GPIO_ATMEL_SAM3_PORTD_IRQ_PRI,
gpio_sam3_isr, DEVICE_GET(gpio_sam3_d), 0);

18
drivers/gpio/gpio_dw.c
View file

@ -85,8 +85,8 @@ static void dw_set_bit(uint32_t base_addr, uint32_t offset,
#ifdef CONFIG_GPIO_DW_CLOCK_GATE
static inline void _gpio_dw_clock_config(struct device *port)
{
struct device *clk;
char *drv = CONFIG_GPIO_DW_CLOCK_GATE_DRV_NAME;
struct device *clk;
clk = device_get_binding(drv);
if (clk) {
@ -176,10 +176,12 @@ static inline void dw_pin_config(struct device *port,
/* set direction */
dw_set_bit(base_addr, SWPORTA_DDR, pin, (flags & GPIO_DIR_MASK));
if (flags & GPIO_INT)
if (flags & GPIO_INT) {
dw_interrupt_config(port, GPIO_ACCESS_BY_PIN, pin, flags);
}
}
static inline void dw_port_config(struct device *port, int flags)
{
struct gpio_dw_config *config = port->config->config_info;
@ -203,6 +205,7 @@ static inline int gpio_dw_config(struct device *port, int access_op,
} else {
dw_port_config(port, flags);
}
return 0;
}
@ -232,6 +235,7 @@ static inline int gpio_dw_read(struct device *port, int access_op,
if (GPIO_ACCESS_BY_PIN == access_op) {
*value = !!(*value & BIT(pin));
}
return 0;
}
@ -257,6 +261,7 @@ static inline int gpio_dw_enable_callback(struct device *port, int access_op,
} else {
context->port_callback = 1;
}
dw_write(base_addr, PORTA_EOI, BIT(pin));
dw_set_bit(base_addr, INTMASK, pin, 0);
@ -275,6 +280,7 @@ static inline int gpio_dw_disable_callback(struct device *port, int access_op,
} else {
context->port_callback = 0;
}
dw_set_bit(base_addr, INTMASK, pin, 1);
return 0;
@ -341,7 +347,7 @@ void gpio_dw_isr(void *arg)
if (context->enabled_callbacks) {
enabled_int = int_status & context->enabled_callbacks;
for (bit = 0; bit < config->bits; bit++) {
if (enabled_int & (1 << bit)) {
if (enabled_int & BIT(bit)) {
context->callback(port, bit);
}
}
@ -484,7 +490,8 @@ void gpio_config_0_irq(struct device *port)
irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_0_IRQ_SHARED)
shared_irq_dev = device_get_binding(config->shared_irq_dev_name);
__ASSERT(shared_irq_dev != NULL, "Failed to get gpio_dw_0 device binding");
__ASSERT(shared_irq_dev != NULL,
"Failed to get gpio_dw_0 device binding");
shared_irq_isr_register(shared_irq_dev, (isr_t)gpio_dw_isr, port);
shared_irq_enable(shared_irq_dev, port);
#endif
@ -558,7 +565,8 @@ void gpio_config_1_irq(struct device *port)
irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_1_IRQ_SHARED)
shared_irq_dev = device_get_binding(config->shared_irq_dev_name);
__ASSERT(shared_irq_dev != NULL, "Failed to get gpio_dw_1 device binding");
__ASSERT(shared_irq_dev != NULL,
"Failed to get gpio_dw_1 device binding");
shared_irq_isr_register(shared_irq_dev, (isr_t)gpio_dw_isr, port);
shared_irq_enable(shared_irq_dev, port);
#endif

102
drivers/gpio/gpio_k64.c
View file

@ -31,8 +31,8 @@
#include "gpio_k64.h"
static int gpio_k64_config(struct device *dev, int access_op,
uint32_t pin, int flags)
static int gpio_k64_config(struct device *dev,
int access_op, uint32_t pin, int flags)
{
const struct gpio_k64_config * const cfg = dev->config->config_info;
uint32_t value;
@ -40,7 +40,6 @@ static int gpio_k64_config(struct device *dev, int access_op,
uint8_t i;
/* check for an invalid pin configuration */
if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
return -ENOTSUP;
@ -50,30 +49,27 @@ static int gpio_k64_config(struct device *dev, int access_op,
* Setup direction register:
* 0 - pin is input, 1 - pin is output
*/
if (access_op == GPIO_ACCESS_BY_PIN) {
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
sys_clear_bit((cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET), pin);
sys_clear_bit((cfg->gpio_base_addr +
GPIO_K64_DIR_OFFSET), pin);
} else { /* GPIO_DIR_OUT */
sys_set_bit((cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET), pin);
sys_set_bit((cfg->gpio_base_addr +
GPIO_K64_DIR_OFFSET), pin);
}
} else { /* GPIO_ACCESS_BY_PORT */
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
value = 0x0;
} else { /* GPIO_DIR_OUT */
value = 0xFFFFFFFF;
}
sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET));
sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET));
}
/*
* Set up pullup/pulldown configuration, in Port Control module:
*/
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_UP);
} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
@ -87,13 +83,9 @@ static int gpio_k64_config(struct device *dev, int access_op,
/*
* Set up interrupt configuration, in Port Control module:
*/
if (flags & GPIO_INT) {
/* edge or level */
if (flags & GPIO_INT_EDGE) {
if (flags & GPIO_INT_ACTIVE_HIGH) {
setting |= K64_PINMUX_INT_RISING;
} else if (flags & GPIO_INT_DOUBLE_EDGE) {
@ -101,26 +93,21 @@ static int gpio_k64_config(struct device *dev, int access_op,
} else {
setting |= K64_PINMUX_INT_FALLING;
}
} else { /* GPIO_INT_LEVEL */
if (flags & GPIO_INT_ACTIVE_HIGH) {
setting |= K64_PINMUX_INT_HIGH;
} else {
setting |= K64_PINMUX_INT_LOW;
}
}
}
/* write pull-up/-down and, if set, interrupt configuration settings */
if (access_op == GPIO_ACCESS_BY_PIN) {
value = sys_read32((cfg->port_base_addr + K64_PINMUX_CTRL_OFFSET(pin)));
value = sys_read32((cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(pin)));
/* clear, then set configuration values */
value &= ~(K64_PINMUX_PULL_EN_MASK | K64_PINMUX_PULL_SEL_MASK);
if (flags & GPIO_INT) {
@ -129,19 +116,16 @@ static int gpio_k64_config(struct device *dev, int access_op,
value |= setting;
sys_write32(value,
(cfg->port_base_addr + K64_PINMUX_CTRL_OFFSET(pin)));
sys_write32(value, (cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(pin)));
} else { /* GPIO_ACCESS_BY_PORT */
for (i = 0; i < K64_PINMUX_NUM_PINS; i++) {
/* clear, then set configuration values */
value = sys_read32((cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(i)));
value &= ~(K64_PINMUX_PULL_EN_MASK | K64_PINMUX_PULL_SEL_MASK);
value &= ~(K64_PINMUX_PULL_EN_MASK |
K64_PINMUX_PULL_SEL_MASK);
if (flags & GPIO_INT) {
value &= ~K64_PINMUX_INT_MASK;
@ -149,9 +133,8 @@ static int gpio_k64_config(struct device *dev, int access_op,
value |= setting;
sys_write32(value,
(cfg->port_base_addr + K64_PINMUX_CTRL_OFFSET(i)));
sys_write32(value, (cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(i)));
}
}
@ -159,40 +142,37 @@ static int gpio_k64_config(struct device *dev, int access_op,
}
static int gpio_k64_write(struct device *dev, int access_op,
uint32_t pin, uint32_t value)
static int gpio_k64_write(struct device *dev,
int access_op, uint32_t pin, uint32_t value)
{
const struct gpio_k64_config * const cfg = dev->config->config_info;
if (access_op == GPIO_ACCESS_BY_PIN) {
if (value) {
sys_set_bit((cfg->gpio_base_addr + GPIO_K64_DATA_OUT_OFFSET),
pin);
sys_set_bit((cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET), pin);
} else {
sys_clear_bit((cfg->gpio_base_addr + GPIO_K64_DATA_OUT_OFFSET),
pin);
sys_clear_bit((cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET), pin);
}
} else { /* GPIO_ACCESS_BY_PORT */
sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DATA_OUT_OFFSET));
sys_write32(value, (cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET));
}
return 0;
}
static int gpio_k64_read(struct device *dev, int access_op,
uint32_t pin, uint32_t *value)
static int gpio_k64_read(struct device *dev,
int access_op, uint32_t pin, uint32_t *value)
{
const struct gpio_k64_config * const cfg = dev->config->config_info;
*value = sys_read32((cfg->gpio_base_addr + GPIO_K64_DATA_IN_OFFSET));
if (access_op == GPIO_ACCESS_BY_PIN) {
*value = (*value & (1 << pin)) >> pin;
*value = (*value & BIT(pin)) >> pin;
}
/* nothing more to do for GPIO_ACCESS_BY_PORT */
@ -211,13 +191,13 @@ static int gpio_k64_set_callback(struct device *dev, gpio_callback_t callback)
}
static int gpio_k64_enable_callback(struct device *dev, int access_op,
uint32_t pin)
static int gpio_k64_enable_callback(struct device *dev,
int access_op, uint32_t pin)
{
struct gpio_k64_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables |= (1 << pin);
data->pin_callback_enables |= BIT(pin);
} else {
data->port_callback_enable = 1;
}
@ -226,13 +206,13 @@ static int gpio_k64_enable_callback(struct device *dev, int access_op,
}
static int gpio_k64_disable_callback(struct device *dev, int access_op,
uint32_t pin)
static int gpio_k64_disable_callback(struct device *dev,
int access_op, uint32_t pin)
{
struct gpio_k64_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables &= ~(1 << pin);
data->pin_callback_enables &= ~BIT(pin);
} else {
data->port_callback_enable = 0;
}
@ -281,33 +261,25 @@ static void gpio_k64_port_isr(void *dev)
int_status = sys_read32(int_status_reg_addr);
if (data->port_callback_enable) {
data->callback_func(port, int_status);
} else if (data->pin_callback_enables) {
/* perform callback for each callback-enabled pin with an interrupt */
/* perform callback for each callback-enabled pin with
* an interrupt
*/
enabled_int = int_status & data->pin_callback_enables;
while ((pin = find_lsb_set(enabled_int))) {
pin--; /* normalize the pin number */
data->callback_func(port, (1 << pin));
data->callback_func(port, BIT(pin));
/* clear the interrupt status */
enabled_int &= ~(1 << pin);
enabled_int &= ~BIT(pin);
}
}
/* clear the port interrupts */
sys_write32(0xFFFFFFFF, int_status_reg_addr);
}

13
drivers/gpio/gpio_k64.h
View file

@ -26,13 +26,12 @@
#include <gpio.h>
/* GPIO Port Register offsets */
#define GPIO_K64_DATA_OUT_OFFSET 0x00 /* Port Data Output Reg. offset */
#define GPIO_K64_SET_OUT_OFFSET 0x04 /* Port Set Output Reg. offset */
#define GPIO_K64_CLR_OUT_OFFSET 0x08 /* Port Clear Output Reg. offset */
#define GPIO_K64_TOGGLE_OUT_OFFSET 0x0C /* Port Toggle Output Reg. offset */
#define GPIO_K64_DATA_IN_OFFSET 0x10 /* Port Data Input Reg. offset */
#define GPIO_K64_DIR_OFFSET 0x14 /* Port Data Direction Reg. offset */
#define GPIO_K64_DATA_OUT_OFFSET 0x00 /* Port Data Output */
#define GPIO_K64_SET_OUT_OFFSET 0x04 /* Port Set Output */
#define GPIO_K64_CLR_OUT_OFFSET 0x08 /* Port Clear Output */
#define GPIO_K64_TOGGLE_OUT_OFFSET 0x0C /* Port Toggle Output */
#define GPIO_K64_DATA_IN_OFFSET 0x10 /* Port Data Input */
#define GPIO_K64_DIR_OFFSET 0x14 /* Port Data Direction */
/** Configuration data */

17
drivers/gpio/gpio_mmio.c
View file

@ -102,8 +102,8 @@ static uint32_t _io_write(uint32_t addr, uint32_t bit, uint32_t value)
*
* @return 0 if successful, failed otherwise
*/
static int gpio_mmio_config(struct device *dev, int access_op,
uint32_t pin, int flags)
static int gpio_mmio_config(struct device *dev,
int access_op, uint32_t pin, int flags)
{
const struct gpio_mmio_config * const cfg =
dev->config->config_info;
@ -224,8 +224,8 @@ static int gpio_mmio_write(struct device *dev, int access_op,
*
* @return 0 if successful, failed otherwise
*/
static int gpio_mmio_read(struct device *dev, int access_op,
uint32_t pin, uint32_t *value)
static int gpio_mmio_read(struct device *dev,
int access_op, uint32_t pin, uint32_t *value)
{
const struct gpio_mmio_config * const cfg =
dev->config->config_info;
@ -237,7 +237,7 @@ static int gpio_mmio_read(struct device *dev, int access_op,
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
*value = cfg->access.read(cfg->reg.input, 0, 0);
*value &= (1 << pin) >> pin;
*value &= BIT(pin) >> pin;
break;
case GPIO_ACCESS_BY_PORT:
*value = cfg->access.read(cfg->reg.input, 0, 0);
@ -249,8 +249,7 @@ static int gpio_mmio_read(struct device *dev, int access_op,
return 0;
}
static int gpio_mmio_set_callback(struct device *dev,
gpio_callback_t callback)
static int gpio_mmio_set_callback(struct device *dev, gpio_callback_t callback)
{
ARG_UNUSED(dev);
ARG_UNUSED(callback);
@ -341,7 +340,7 @@ static struct gpio_mmio_config gpio_mmio_0_cfg = {
};
DEVICE_INIT(gpio_mmio_0, CONFIG_GPIO_MMIO_0_DEV_NAME, gpio_mmio_init,
(void *)0, &gpio_mmio_0_cfg,
NULL, &gpio_mmio_0_cfg,
SECONDARY, CONFIG_GPIO_MMIO_INIT_PRIORITY);
#endif /* CONFIG_GPIO_MMIO_0 */
@ -371,7 +370,7 @@ static struct gpio_mmio_config gpio_mmio_1_cfg = {
};
DEVICE_INIT(gpio_mmio_1, CONFIG_GPIO_MMIO_1_DEV_NAME, gpio_mmio_init,
(void *)0, &gpio_mmio_1_cfg,
NULL, &gpio_mmio_1_cfg,
SECONDARY, CONFIG_GPIO_MMIO_INIT_PRIORITY);
#endif /* CONFIG_GPIO_MMIO_1 */

12
drivers/gpio/gpio_mmio.h
View file

@ -33,17 +33,17 @@ extern "C" {
* NORMAL: 0 - disable, 1 - enable
* INV: 0 - enable, 1 - disable
*/
#define GPIO_MMIO_CFG_EN_NORMAL (0 << 0)
#define GPIO_MMIO_CFG_EN_INV (1 << 0)
#define GPIO_MMIO_CFG_EN_MASK (1 << 0)
#define GPIO_MMIO_CFG_EN_NORMAL (0)
#define GPIO_MMIO_CFG_EN_INV BIT(0)
#define GPIO_MMIO_CFG_EN_MASK BIT(0)
/* For direction register:
* NORMAL: 0 - pin is output, 1 - pin is input
* INV: 0 - pin is input, 1 - pin is output
*/
#define GPIO_MMIO_CFG_DIR_NORMAL (0 << 1)
#define GPIO_MMIO_CFG_DIR_INV (1 << 1)
#define GPIO_MMIO_CFG_DIR_MASK (1 << 1)
#define GPIO_MMIO_CFG_DIR_NORMAL (0)
#define GPIO_MMIO_CFG_DIR_INV BIT(1)
#define GPIO_MMIO_CFG_DIR_MASK BIT(1)
/**
* @brief Initialization function for GPIO driver

8
drivers/gpio/gpio_pcal9535a.c
View file

@ -22,6 +22,7 @@
#include <nanokernel.h>
#include <misc/util.h>
#include <gpio.h>
#include <i2c.h>
@ -330,11 +331,11 @@ static int _setup_pin_polarity(struct device *dev, int access_op,
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
bit_mask = 1 << pin;
bit_mask = BIT(pin);
/* normal == 0, invert == 1 */
if ((flags & GPIO_POL_MASK) == GPIO_POL_INV) {
new_value = 1 << pin;
new_value = BIT(pin);
}
port->all &= ~bit_mask;
@ -440,7 +441,7 @@ static int gpio_pcal9535a_write(struct device *dev, int access_op,
/* Invert input value for pins configurated as active low. */
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
bit_mask = 1 << pin;
bit_mask = BIT(pin);
new_value = (value << pin) & bit_mask;
new_value ^= (drv_data->out_pol_inv & bit_mask);
@ -706,5 +707,4 @@ DEVICE_INIT(gpio_pcal9535a_3, CONFIG_GPIO_PCAL9535A_3_DEV_NAME,
&gpio_pcal9535a_3_drvdata, &gpio_pcal9535a_3_cfg,
SECONDARY, CONFIG_GPIO_PCAL9535A_INIT_PRIORITY);
#endif /* CONFIG_GPIO_PCAL9535A_3 */

39
drivers/gpio/gpio_qmsi.c
View file

@ -79,19 +79,21 @@ static void gpio_qmsi_callback(struct device *port, uint32_t status)
const uint32_t enabled_mask = context->pin_callbacks & status;
int bit;
if (!context->callback)
if (!context->callback) {
return;
}
if (context->port_callback) {
context->callback(port, status);
return;
}
if (!enabled_mask)
if (!enabled_mask) {
return;
}
for (bit = 0; bit < config->num_pins; bit++) {
if (enabled_mask & (1 << bit)) {
if (enabled_mask & BIT(bit)) {
context->callback(port, bit);
}
}
@ -143,9 +145,12 @@ static inline void qmsi_pin_config(struct device *port, uint32_t pin, int flags)
if (flags & GPIO_INT) {
qmsi_write_bit(&cfg.int_type, pin, (flags & GPIO_INT_EDGE));
qmsi_write_bit(&cfg.int_polarity, pin, (flags & GPIO_INT_ACTIVE_HIGH));
qmsi_write_bit(&cfg.int_debounce, pin, (flags & GPIO_INT_DEBOUNCE));
qmsi_write_bit(&cfg.int_bothedge, pin, (flags & GPIO_INT_DOUBLE_EDGE));
qmsi_write_bit(&cfg.int_polarity, pin,
(flags & GPIO_INT_ACTIVE_HIGH));
qmsi_write_bit(&cfg.int_debounce, pin,
(flags & GPIO_INT_DEBOUNCE));
qmsi_write_bit(&cfg.int_bothedge, pin,
(flags & GPIO_INT_DOUBLE_EDGE));
qmsi_write_bit(&cfg.int_en, pin, 1);
}
@ -178,8 +183,8 @@ static inline void qmsi_port_config(struct device *port, int flags)
}
}
static inline int gpio_qmsi_config(struct device *port, int access_op,
uint32_t pin, int flags)
static inline int gpio_qmsi_config(struct device *port,
int access_op, uint32_t pin, int flags)
{
if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
@ -194,8 +199,8 @@ static inline int gpio_qmsi_config(struct device *port, int access_op,
return 0;
}
static inline int gpio_qmsi_write(struct device *port, int access_op,
uint32_t pin, uint32_t value)
static inline int gpio_qmsi_write(struct device *port,
int access_op, uint32_t pin, uint32_t value)
{
struct gpio_qmsi_config *gpio_config = port->config->config_info;
qm_gpio_t gpio = gpio_config->gpio;
@ -213,8 +218,8 @@ static inline int gpio_qmsi_write(struct device *port, int access_op,
return 0;
}
static inline int gpio_qmsi_read(struct device *port, int access_op,
uint32_t pin, uint32_t *value)
static inline int gpio_qmsi_read(struct device *port,
int access_op, uint32_t pin, uint32_t *value)
{
struct gpio_qmsi_config *gpio_config = port->config->config_info;
qm_gpio_t gpio = gpio_config->gpio;
@ -238,8 +243,8 @@ static inline int gpio_qmsi_set_callback(struct device *port,
return 0;
}
static inline int gpio_qmsi_enable_callback(struct device *port, int access_op,
uint32_t pin)
static inline int gpio_qmsi_enable_callback(struct device *port,
int access_op, uint32_t pin)
{
struct gpio_qmsi_runtime *context = port->driver_data;
@ -252,8 +257,8 @@ static inline int gpio_qmsi_enable_callback(struct device *port, int access_op,
return 0;
}
static inline int gpio_qmsi_disable_callback(struct device *port, int access_op,
uint32_t pin)
static inline int gpio_qmsi_disable_callback(struct device *port,
int access_op, uint32_t pin)
{
struct gpio_qmsi_runtime *context = port->driver_data;
@ -303,7 +308,6 @@ int gpio_qmsi_init(struct device *port)
irq_enable(CONFIG_GPIO_QMSI_0_IRQ);
QM_SCSS_INT->int_gpio_mask &= ~BIT(0);
break;
#ifdef CONFIG_GPIO_QMSI_AON
case QM_AON_GPIO_0:
IRQ_CONNECT(CONFIG_GPIO_QMSI_AON_IRQ,
@ -313,7 +317,6 @@ int gpio_qmsi_init(struct device *port)
QM_SCSS_INT->int_aon_gpio_mask &= ~BIT(0);
break;
#endif /* CONFIG_GPIO_QMSI_AON */
default:
return -EIO;
}

6
drivers/gpio/gpio_sch.c
View file

@ -97,8 +97,7 @@ static inline void _set_data_reg(uint32_t *reg, uint8_t pin, uint8_t set)
*reg |= (set << pin) & BIT(pin);
}
static void _gpio_pin_config(struct device *dev,
uint32_t pin, int flags)
static void _gpio_pin_config(struct device *dev, uint32_t pin, int flags)
{
struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data;
@ -240,8 +239,7 @@ loop:
}
}
static int gpio_sch_set_callback(struct device *dev,
gpio_callback_t callback)
static int gpio_sch_set_callback(struct device *dev, gpio_callback_t callback)
{
struct gpio_sch_data *gpio = dev->driver_data;

10
drivers/gpio/gpio_stm32.c
View file

@ -45,7 +45,7 @@ static void gpio_stm32_isr(int line, void *arg)
return;
}
is_enabled = data->enabled_mask & (1 << line);
is_enabled = data->enabled_mask & BIT(line);
if (!is_enabled) {
return;
@ -91,12 +91,14 @@ static int gpio_stm32_config(struct device *dev, int access_op,
int edge = 0;
if (flags & GPIO_INT_DOUBLE_EDGE) {
edge = STM32_EXTI_TRIG_RISING | STM32_EXTI_TRIG_FALLING;
edge = STM32_EXTI_TRIG_RISING |
STM32_EXTI_TRIG_FALLING;
} else if (flags & GPIO_INT_ACTIVE_HIGH) {
edge = STM32_EXTI_TRIG_RISING;
} else {
edge = STM32_EXTI_TRIG_FALLING;
}
stm32_exti_trigger(exti, pin, edge);
}
@ -157,7 +159,7 @@ static int gpio_stm32_enable_callback(struct device *dev,
return -ENOTSUP;
}
data->enabled_mask |= 1 << pin;
data->enabled_mask |= BIT(pin);
return 0;
}
@ -171,7 +173,7 @@ static int gpio_stm32_disable_callback(struct device *dev,
return -ENOTSUP;
}
data->enabled_mask &= ~(1 << pin);
data->enabled_mask &= ~BIT(pin);
return 0;
}