michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: gpio: Align the style all over the drivers

Browse source 
Fixing:
- indentation
- 80 chars limit
- { } mandatory on relevant statements
- using BIT() macro relevantly

Change-Id: Ib84eb29530b175c8a533c1b361aea2632f0d7917
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2016-03-23 10:53:04 +01:00 • committed by Gerrit Code Review
commit 67196bc0c3
10 changed files with 177 additions and 196 deletions
Download patch file Download diff file Expand all files Collapse all files

20
drivers/gpio/gpio_atmel_sam3.c
View file

@ -117,7 +117,7 @@ static int gpio_sam3_config(struct device *dev, int access_op,
{ {
switch (access_op) { switch (access_op) {
case GPIO_ACCESS_BY_PIN: case GPIO_ACCESS_BY_PIN:
_config(dev, (1 << pin), flags); _config(dev, BIT(pin), flags);
break; break;
case GPIO_ACCESS_BY_PORT: case GPIO_ACCESS_BY_PORT:
_config(dev, (0xFFFFFFFF), flags); _config(dev, (0xFFFFFFFF), flags);
@ -148,10 +148,10 @@ static int gpio_sam3_write(struct device *dev, int access_op,
case GPIO_ACCESS_BY_PIN: case GPIO_ACCESS_BY_PIN:
if (value) { if (value) {
/* set the pin */ /* set the pin */
cfg->port->sodr = (1 << pin); cfg->port->sodr = BIT(pin);
} else { } else {
/* clear the pin */ /* clear the pin */
cfg->port->codr = (1 << pin); cfg->port->codr = BIT(pin);
} }
break; break;
case GPIO_ACCESS_BY_PORT: case GPIO_ACCESS_BY_PORT:
@ -221,7 +221,7 @@ static void gpio_sam3_isr(void *arg)
int_stat &= cfg->enabled_cb; int_stat &= cfg->enabled_cb;
for (bit = 0; bit < 32; bit++) { for (bit = 0; bit < 32; bit++) {
if (int_stat & (1 << bit)) { if (int_stat & BIT(bit)) {
cfg->cb(dev, bit); cfg->cb(dev, bit);
} }
} }
@ -246,7 +246,7 @@ static int gpio_sam3_enable_callback(struct device *dev,
switch (access_op) { switch (access_op) {
case GPIO_ACCESS_BY_PIN: case GPIO_ACCESS_BY_PIN:
mask = (1 << pin); mask = BIT(pin);
break; break;
case GPIO_ACCESS_BY_PORT: case GPIO_ACCESS_BY_PORT:
mask = 0xFFFFFFFF; mask = 0xFFFFFFFF;
@ -269,7 +269,7 @@ static int gpio_sam3_disable_callback(struct device *dev,
switch (access_op) { switch (access_op) {
case GPIO_ACCESS_BY_PIN: case GPIO_ACCESS_BY_PIN:
mask = (1 << pin); mask = BIT(pin);
break; break;
case GPIO_ACCESS_BY_PORT: case GPIO_ACCESS_BY_PORT:
mask = 0xFFFFFFFF; mask = 0xFFFFFFFF;
@ -343,7 +343,7 @@ DEVICE_INIT(gpio_sam3_a, CONFIG_GPIO_ATMEL_SAM3_PORTA_DEV_NAME,
void gpio_sam3_config_a(struct device *dev) void gpio_sam3_config_a(struct device *dev)
{ {
/* Enable clock for PIO controller */ /* Enable clock for PIO controller */
__PMC->pcer0 = (1 << PID_PIOA); __PMC->pcer0 = BIT(PID_PIOA);
IRQ_CONNECT(IRQ_PIOA, CONFIG_GPIO_ATMEL_SAM3_PORTA_IRQ_PRI, IRQ_CONNECT(IRQ_PIOA, CONFIG_GPIO_ATMEL_SAM3_PORTA_IRQ_PRI,
gpio_sam3_isr, DEVICE_GET(gpio_sam3_a), 0); gpio_sam3_isr, DEVICE_GET(gpio_sam3_a), 0);
@ -368,7 +368,7 @@ DEVICE_INIT(gpio_sam3_b, CONFIG_GPIO_ATMEL_SAM3_PORTB_DEV_NAME,
void gpio_sam3_config_b(struct device *dev) void gpio_sam3_config_b(struct device *dev)
{ {
/* Enable clock for PIO controller */ /* Enable clock for PIO controller */
__PMC->pcer0 = (1 << PID_PIOB); __PMC->pcer0 = BIT(PID_PIOB);
IRQ_CONNECT(IRQ_PIOB, CONFIG_GPIO_ATMEL_SAM3_PORTB_IRQ_PRI, IRQ_CONNECT(IRQ_PIOB, CONFIG_GPIO_ATMEL_SAM3_PORTB_IRQ_PRI,
gpio_sam3_isr, DEVICE_GET(gpio_sam3_b), 0); gpio_sam3_isr, DEVICE_GET(gpio_sam3_b), 0);
@ -393,7 +393,7 @@ DEVICE_INIT(gpio_sam3_c, CONFIG_GPIO_ATMEL_SAM3_PORTC_DEV_NAME,
void gpio_sam3_config_c(struct device *dev) void gpio_sam3_config_c(struct device *dev)
{ {
/* Enable clock for PIO controller */ /* Enable clock for PIO controller */
__PMC->pcer0 = (1 << PID_PIOC); __PMC->pcer0 = BIT(PID_PIOC);
IRQ_CONNECT(IRQ_PIOC, CONFIG_GPIO_ATMEL_SAM3_PORTC_IRQ_PRI, IRQ_CONNECT(IRQ_PIOC, CONFIG_GPIO_ATMEL_SAM3_PORTC_IRQ_PRI,
gpio_sam3_isr, DEVICE_GET(gpio_sam3_c), 0); gpio_sam3_isr, DEVICE_GET(gpio_sam3_c), 0);
@ -418,7 +418,7 @@ DEVICE_INIT(gpio_sam3_d, CONFIG_GPIO_ATMEL_SAM3_PORTD_DEV_NAME,
void gpio_sam3_config_d(struct device *dev) void gpio_sam3_config_d(struct device *dev)
{ {
/* Enable clock for PIO controller */ /* Enable clock for PIO controller */
__PMC->pcer0 = (1 << PID_PIOD); __PMC->pcer0 = BIT(PID_PIOD);
IRQ_CONNECT(IRQ_PIOD, CONFIG_GPIO_ATMEL_SAM3_PORTD_IRQ_PRI, IRQ_CONNECT(IRQ_PIOD, CONFIG_GPIO_ATMEL_SAM3_PORTD_IRQ_PRI,
gpio_sam3_isr, DEVICE_GET(gpio_sam3_d), 0); gpio_sam3_isr, DEVICE_GET(gpio_sam3_d), 0);

40
drivers/gpio/gpio_dw.c
View file

@ -45,13 +45,13 @@ static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset)
} }
static inline void dw_write(uint32_t base_addr, uint32_t offset, static inline void dw_write(uint32_t base_addr, uint32_t offset,
uint32_t val) uint32_t val)
{ {
sys_out32(val, base_addr + offset); sys_out32(val, base_addr + offset);
} }
static void dw_set_bit(uint32_t base_addr, uint32_t offset, static void dw_set_bit(uint32_t base_addr, uint32_t offset,
uint32_t bit, uint8_t value) uint32_t bit, uint8_t value)
{ {
if (!value) { if (!value) {
sys_io_clear_bit(base_addr + offset, bit); sys_io_clear_bit(base_addr + offset, bit);
@ -66,13 +66,13 @@ static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset)
} }
static inline void dw_write(uint32_t base_addr, uint32_t offset, static inline void dw_write(uint32_t base_addr, uint32_t offset,
uint32_t val) uint32_t val)
{ {
sys_write32(val, base_addr + offset); sys_write32(val, base_addr + offset);
} }
static void dw_set_bit(uint32_t base_addr, uint32_t offset, static void dw_set_bit(uint32_t base_addr, uint32_t offset,
uint32_t bit, uint8_t value) uint32_t bit, uint8_t value)
{ {
if (!value) { if (!value) {
sys_clear_bit(base_addr + offset, bit); sys_clear_bit(base_addr + offset, bit);
@ -85,8 +85,8 @@ static void dw_set_bit(uint32_t base_addr, uint32_t offset,
#ifdef CONFIG_GPIO_DW_CLOCK_GATE #ifdef CONFIG_GPIO_DW_CLOCK_GATE
static inline void _gpio_dw_clock_config(struct device *port) static inline void _gpio_dw_clock_config(struct device *port)
{ {
struct device *clk;
char *drv = CONFIG_GPIO_DW_CLOCK_GATE_DRV_NAME; char *drv = CONFIG_GPIO_DW_CLOCK_GATE_DRV_NAME;
struct device *clk;
clk = device_get_binding(drv); clk = device_get_binding(drv);
if (clk) { if (clk) {
@ -131,7 +131,7 @@ static inline void dw_set_both_edges(uint32_t base_addr, uint32_t pin)
#endif #endif
static inline void dw_interrupt_config(struct device *port, int access_op, static inline void dw_interrupt_config(struct device *port, int access_op,
uint32_t pin, int flags) uint32_t pin, int flags)
{ {
struct gpio_dw_config *config = port->config->config_info; struct gpio_dw_config *config = port->config->config_info;
uint32_t base_addr = config->base_addr; uint32_t base_addr = config->base_addr;
@ -165,7 +165,7 @@ static inline void dw_interrupt_config(struct device *port, int access_op,
} }
static inline void dw_pin_config(struct device *port, static inline void dw_pin_config(struct device *port,
uint32_t pin, int flags) uint32_t pin, int flags)
{ {
struct gpio_dw_config *config = port->config->config_info; struct gpio_dw_config *config = port->config->config_info;
uint32_t base_addr = config->base_addr; uint32_t base_addr = config->base_addr;
@ -176,8 +176,10 @@ static inline void dw_pin_config(struct device *port,
/* set direction */ /* set direction */
dw_set_bit(base_addr, SWPORTA_DDR, pin, (flags & GPIO_DIR_MASK)); dw_set_bit(base_addr, SWPORTA_DDR, pin, (flags & GPIO_DIR_MASK));
if (flags & GPIO_INT) if (flags & GPIO_INT) {
dw_interrupt_config(port, GPIO_ACCESS_BY_PIN, pin, flags); dw_interrupt_config(port, GPIO_ACCESS_BY_PIN, pin, flags);
}
} }
static inline void dw_port_config(struct device *port, int flags) static inline void dw_port_config(struct device *port, int flags)
@ -203,6 +205,7 @@ static inline int gpio_dw_config(struct device *port, int access_op,
} else { } else {
dw_port_config(port, flags); dw_port_config(port, flags);
} }
return 0; return 0;
} }
@ -222,7 +225,7 @@ static inline int gpio_dw_write(struct device *port, int access_op,
} }
static inline int gpio_dw_read(struct device *port, int access_op, static inline int gpio_dw_read(struct device *port, int access_op,
uint32_t pin, uint32_t *value) uint32_t pin, uint32_t *value)
{ {
struct gpio_dw_config *config = port->config->config_info; struct gpio_dw_config *config = port->config->config_info;
uint32_t base_addr = config->base_addr; uint32_t base_addr = config->base_addr;
@ -232,6 +235,7 @@ static inline int gpio_dw_read(struct device *port, int access_op,
if (GPIO_ACCESS_BY_PIN == access_op) { if (GPIO_ACCESS_BY_PIN == access_op) {
*value = !!(*value & BIT(pin)); *value = !!(*value & BIT(pin));
} }
return 0; return 0;
} }
@ -257,6 +261,7 @@ static inline int gpio_dw_enable_callback(struct device *port, int access_op,
} else { } else {
context->port_callback = 1; context->port_callback = 1;
} }
dw_write(base_addr, PORTA_EOI, BIT(pin)); dw_write(base_addr, PORTA_EOI, BIT(pin));
dw_set_bit(base_addr, INTMASK, pin, 0); dw_set_bit(base_addr, INTMASK, pin, 0);
@ -275,6 +280,7 @@ static inline int gpio_dw_disable_callback(struct device *port, int access_op,
} else { } else {
context->port_callback = 0; context->port_callback = 0;
} }
dw_set_bit(base_addr, INTMASK, pin, 1); dw_set_bit(base_addr, INTMASK, pin, 1);
return 0; return 0;
@ -341,7 +347,7 @@ void gpio_dw_isr(void *arg)
if (context->enabled_callbacks) { if (context->enabled_callbacks) {
enabled_int = int_status & context->enabled_callbacks; enabled_int = int_status & context->enabled_callbacks;
for (bit = 0; bit < config->bits; bit++) { for (bit = 0; bit < config->bits; bit++) {
if (enabled_int & (1 << bit)) { if (enabled_int & BIT(bit)) {
context->callback(port, bit); context->callback(port, bit);
} }
} }
@ -451,8 +457,8 @@ struct gpio_dw_config gpio_config_0 = {
struct gpio_dw_runtime gpio_0_runtime; struct gpio_dw_runtime gpio_0_runtime;
DEVICE_INIT(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize, DEVICE_INIT(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize,
&gpio_0_runtime, &gpio_config_0, &gpio_0_runtime, &gpio_config_0,
SECONDARY, CONFIG_GPIO_DW_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_DW_INIT_PRIORITY);
#ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT
#ifdef CONFIG_IOAPIC #ifdef CONFIG_IOAPIC
@ -484,7 +490,8 @@ void gpio_config_0_irq(struct device *port)
irq_enable(config->irq_num); irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_0_IRQ_SHARED) #elif defined(CONFIG_GPIO_DW_0_IRQ_SHARED)
shared_irq_dev = device_get_binding(config->shared_irq_dev_name); shared_irq_dev = device_get_binding(config->shared_irq_dev_name);
__ASSERT(shared_irq_dev != NULL, "Failed to get gpio_dw_0 device binding"); __ASSERT(shared_irq_dev != NULL,
"Failed to get gpio_dw_0 device binding");
shared_irq_isr_register(shared_irq_dev, (isr_t)gpio_dw_isr, port); shared_irq_isr_register(shared_irq_dev, (isr_t)gpio_dw_isr, port);
shared_irq_enable(shared_irq_dev, port); shared_irq_enable(shared_irq_dev, port);
#endif #endif
@ -525,8 +532,8 @@ struct gpio_dw_config gpio_dw_config_1 = {
struct gpio_dw_runtime gpio_1_runtime; struct gpio_dw_runtime gpio_1_runtime;
DEVICE_INIT(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize, DEVICE_INIT(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize,
&gpio_1_runtime, &gpio_dw_config_1, &gpio_1_runtime, &gpio_dw_config_1,
SECONDARY, CONFIG_GPIO_DW_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_DW_INIT_PRIORITY);
#ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT
#ifdef CONFIG_IOAPIC #ifdef CONFIG_IOAPIC
@ -558,7 +565,8 @@ void gpio_config_1_irq(struct device *port)
irq_enable(config->irq_num); irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_1_IRQ_SHARED) #elif defined(CONFIG_GPIO_DW_1_IRQ_SHARED)
shared_irq_dev = device_get_binding(config->shared_irq_dev_name); shared_irq_dev = device_get_binding(config->shared_irq_dev_name);
__ASSERT(shared_irq_dev != NULL, "Failed to get gpio_dw_1 device binding"); __ASSERT(shared_irq_dev != NULL,
"Failed to get gpio_dw_1 device binding");
shared_irq_isr_register(shared_irq_dev, (isr_t)gpio_dw_isr, port); shared_irq_isr_register(shared_irq_dev, (isr_t)gpio_dw_isr, port);
shared_irq_enable(shared_irq_dev, port); shared_irq_enable(shared_irq_dev, port);
#endif #endif

142
drivers/gpio/gpio_k64.c
View file

@ -31,8 +31,8 @@
#include "gpio_k64.h" #include "gpio_k64.h"
static int gpio_k64_config(struct device *dev, int access_op, static int gpio_k64_config(struct device *dev,
uint32_t pin, int flags) int access_op, uint32_t pin, int flags)
{ {
const struct gpio_k64_config * const cfg = dev->config->config_info; const struct gpio_k64_config * const cfg = dev->config->config_info;
uint32_t value; uint32_t value;
@ -40,9 +40,8 @@ static int gpio_k64_config(struct device *dev, int access_op,
uint8_t i; uint8_t i;
/* check for an invalid pin configuration */ /* check for an invalid pin configuration */
if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) || if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) { ((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
return -ENOTSUP; return -ENOTSUP;
} }
@ -50,30 +49,27 @@ static int gpio_k64_config(struct device *dev, int access_op,
* Setup direction register: * Setup direction register:
* 0 - pin is input, 1 - pin is output * 0 - pin is input, 1 - pin is output
*/ */
if (access_op == GPIO_ACCESS_BY_PIN) { if (access_op == GPIO_ACCESS_BY_PIN) {
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) { if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
sys_clear_bit((cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET), pin); sys_clear_bit((cfg->gpio_base_addr +
GPIO_K64_DIR_OFFSET), pin);
} else { /* GPIO_DIR_OUT */ } else { /* GPIO_DIR_OUT */
sys_set_bit((cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET), pin); sys_set_bit((cfg->gpio_base_addr +
GPIO_K64_DIR_OFFSET), pin);
} }
} else { /* GPIO_ACCESS_BY_PORT */ } else { /* GPIO_ACCESS_BY_PORT */
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) { if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
value = 0x0; value = 0x0;
} else { /* GPIO_DIR_OUT */ } else { /* GPIO_DIR_OUT */
value = 0xFFFFFFFF; value = 0xFFFFFFFF;
} }
sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET));
sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET));
} }
/* /*
* Set up pullup/pulldown configuration, in Port Control module: * Set up pullup/pulldown configuration, in Port Control module:
*/ */
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) { if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_UP); setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_UP);
} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) { } else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
@ -87,13 +83,9 @@ static int gpio_k64_config(struct device *dev, int access_op,
/* /*
* Set up interrupt configuration, in Port Control module: * Set up interrupt configuration, in Port Control module:
*/ */
if (flags & GPIO_INT) { if (flags & GPIO_INT) {
/* edge or level */ /* edge or level */
if (flags & GPIO_INT_EDGE) { if (flags & GPIO_INT_EDGE) {
if (flags & GPIO_INT_ACTIVE_HIGH) { if (flags & GPIO_INT_ACTIVE_HIGH) {
setting |= K64_PINMUX_INT_RISING; setting |= K64_PINMUX_INT_RISING;
} else if (flags & GPIO_INT_DOUBLE_EDGE) { } else if (flags & GPIO_INT_DOUBLE_EDGE) {
@ -101,26 +93,21 @@ static int gpio_k64_config(struct device *dev, int access_op,
} else { } else {
setting |= K64_PINMUX_INT_FALLING; setting |= K64_PINMUX_INT_FALLING;
} }
} else { /* GPIO_INT_LEVEL */
} else { /* GPIO_INT_LEVEL */
if (flags & GPIO_INT_ACTIVE_HIGH) { if (flags & GPIO_INT_ACTIVE_HIGH) {
setting |= K64_PINMUX_INT_HIGH; setting |= K64_PINMUX_INT_HIGH;
} else { } else {
setting |= K64_PINMUX_INT_LOW; setting |= K64_PINMUX_INT_LOW;
} }
} }
} }
/* write pull-up/-down and, if set, interrupt configuration settings */ /* write pull-up/-down and, if set, interrupt configuration settings */
if (access_op == GPIO_ACCESS_BY_PIN) { if (access_op == GPIO_ACCESS_BY_PIN) {
value = sys_read32((cfg->port_base_addr +
value = sys_read32((cfg->port_base_addr + K64_PINMUX_CTRL_OFFSET(pin))); K64_PINMUX_CTRL_OFFSET(pin)));
/* clear, then set configuration values */ /* clear, then set configuration values */
value &= ~(K64_PINMUX_PULL_EN_MASK | K64_PINMUX_PULL_SEL_MASK); value &= ~(K64_PINMUX_PULL_EN_MASK | K64_PINMUX_PULL_SEL_MASK);
if (flags & GPIO_INT) { if (flags & GPIO_INT) {
@ -129,19 +116,16 @@ static int gpio_k64_config(struct device *dev, int access_op,
value |= setting; value |= setting;
sys_write32(value, sys_write32(value, (cfg->port_base_addr +
(cfg->port_base_addr + K64_PINMUX_CTRL_OFFSET(pin))); K64_PINMUX_CTRL_OFFSET(pin)));
} else { /* GPIO_ACCESS_BY_PORT */ } else { /* GPIO_ACCESS_BY_PORT */
for (i = 0; i < K64_PINMUX_NUM_PINS; i++) { for (i = 0; i < K64_PINMUX_NUM_PINS; i++) {
/* clear, then set configuration values */ /* clear, then set configuration values */
value = sys_read32((cfg->port_base_addr + value = sys_read32((cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(i))); K64_PINMUX_CTRL_OFFSET(i)));
value &= ~(K64_PINMUX_PULL_EN_MASK | K64_PINMUX_PULL_SEL_MASK); value &= ~(K64_PINMUX_PULL_EN_MASK |
K64_PINMUX_PULL_SEL_MASK);
if (flags & GPIO_INT) { if (flags & GPIO_INT) {
value &= ~K64_PINMUX_INT_MASK; value &= ~K64_PINMUX_INT_MASK;
@ -149,9 +133,8 @@ static int gpio_k64_config(struct device *dev, int access_op,
value |= setting; value |= setting;
sys_write32(value, sys_write32(value, (cfg->port_base_addr +
(cfg->port_base_addr + K64_PINMUX_CTRL_OFFSET(i))); K64_PINMUX_CTRL_OFFSET(i)));
} }
} }
@ -159,40 +142,37 @@ static int gpio_k64_config(struct device *dev, int access_op,
} }
static int gpio_k64_write(struct device *dev, int access_op, static int gpio_k64_write(struct device *dev,
uint32_t pin, uint32_t value) int access_op, uint32_t pin, uint32_t value)
{ {
const struct gpio_k64_config * const cfg = dev->config->config_info; const struct gpio_k64_config * const cfg = dev->config->config_info;
if (access_op == GPIO_ACCESS_BY_PIN) { if (access_op == GPIO_ACCESS_BY_PIN) {
if (value) { if (value) {
sys_set_bit((cfg->gpio_base_addr + GPIO_K64_DATA_OUT_OFFSET), sys_set_bit((cfg->gpio_base_addr +
pin); GPIO_K64_DATA_OUT_OFFSET), pin);
} else { } else {
sys_clear_bit((cfg->gpio_base_addr + GPIO_K64_DATA_OUT_OFFSET), sys_clear_bit((cfg->gpio_base_addr +
pin); GPIO_K64_DATA_OUT_OFFSET), pin);
} }
} else { /* GPIO_ACCESS_BY_PORT */
} else { /* GPIO_ACCESS_BY_PORT */ sys_write32(value, (cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET));
sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DATA_OUT_OFFSET));
} }
return 0; return 0;
} }
static int gpio_k64_read(struct device *dev, int access_op, static int gpio_k64_read(struct device *dev,
uint32_t pin, uint32_t *value) int access_op, uint32_t pin, uint32_t *value)
{ {
const struct gpio_k64_config * const cfg = dev->config->config_info; const struct gpio_k64_config * const cfg = dev->config->config_info;
*value = sys_read32((cfg->gpio_base_addr + GPIO_K64_DATA_IN_OFFSET)); *value = sys_read32((cfg->gpio_base_addr + GPIO_K64_DATA_IN_OFFSET));
if (access_op == GPIO_ACCESS_BY_PIN) { if (access_op == GPIO_ACCESS_BY_PIN) {
*value = (*value & (1 << pin)) >> pin; *value = (*value & BIT(pin)) >> pin;
} }
/* nothing more to do for GPIO_ACCESS_BY_PORT */ /* nothing more to do for GPIO_ACCESS_BY_PORT */
@ -211,13 +191,13 @@ static int gpio_k64_set_callback(struct device *dev, gpio_callback_t callback)
} }
static int gpio_k64_enable_callback(struct device *dev, int access_op, static int gpio_k64_enable_callback(struct device *dev,
uint32_t pin) int access_op, uint32_t pin)
{ {
struct gpio_k64_data *data = dev->driver_data; struct gpio_k64_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) { if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables |= (1 << pin); data->pin_callback_enables |= BIT(pin);
} else { } else {
data->port_callback_enable = 1; data->port_callback_enable = 1;
} }
@ -226,13 +206,13 @@ static int gpio_k64_enable_callback(struct device *dev, int access_op,
} }
static int gpio_k64_disable_callback(struct device *dev, int access_op, static int gpio_k64_disable_callback(struct device *dev,
uint32_t pin) int access_op, uint32_t pin)
{ {
struct gpio_k64_data *data = dev->driver_data; struct gpio_k64_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) { if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables &= ~(1 << pin); data->pin_callback_enables &= ~BIT(pin);
} else { } else {
data->port_callback_enable = 0; data->port_callback_enable = 0;
} }
@ -276,38 +256,30 @@ static void gpio_k64_port_isr(void *dev)
} }
int_status_reg_addr = config->port_base_addr + int_status_reg_addr = config->port_base_addr +
CONFIG_PORT_K64_INT_STATUS_OFFSET; CONFIG_PORT_K64_INT_STATUS_OFFSET;
int_status = sys_read32(int_status_reg_addr); int_status = sys_read32(int_status_reg_addr);
if (data->port_callback_enable) { if (data->port_callback_enable) {
data->callback_func(port, int_status); data->callback_func(port, int_status);
} else if (data->pin_callback_enables) { } else if (data->pin_callback_enables) {
/* perform callback for each callback-enabled pin with
/* perform callback for each callback-enabled pin with an interrupt */ * an interrupt
*/
enabled_int = int_status & data->pin_callback_enables; enabled_int = int_status & data->pin_callback_enables;
while ((pin = find_lsb_set(enabled_int))) { while ((pin = find_lsb_set(enabled_int))) {
pin--; /* normalize the pin number */ pin--; /* normalize the pin number */
data->callback_func(port, (1 << pin)); data->callback_func(port, BIT(pin));
/* clear the interrupt status */ /* clear the interrupt status */
enabled_int &= ~BIT(pin);
enabled_int &= ~(1 << pin);
} }
} }
/* clear the port interrupts */ /* clear the port interrupts */
sys_write32(0xFFFFFFFF, int_status_reg_addr); sys_write32(0xFFFFFFFF, int_status_reg_addr);
} }
@ -349,13 +321,13 @@ static struct gpio_k64_config gpio_k64_A_cfg = {
static struct gpio_k64_data gpio_data_A; static struct gpio_k64_data gpio_data_A;
DEVICE_INIT(gpio_k64_A, CONFIG_GPIO_K64_A_DEV_NAME, gpio_k64_A_init, DEVICE_INIT(gpio_k64_A, CONFIG_GPIO_K64_A_DEV_NAME, gpio_k64_A_init,
&gpio_data_A, &gpio_k64_A_cfg, &gpio_data_A, &gpio_k64_A_cfg,
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
static int gpio_k64_A_init(struct device *dev) static int gpio_k64_A_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_K64_PORTA_IRQ, CONFIG_GPIO_K64_PORTA_PRI, IRQ_CONNECT(CONFIG_GPIO_K64_PORTA_IRQ, CONFIG_GPIO_K64_PORTA_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_A), 0); gpio_k64_port_isr, DEVICE_GET(gpio_k64_A), 0);
irq_enable(CONFIG_GPIO_K64_PORTA_IRQ); irq_enable(CONFIG_GPIO_K64_PORTA_IRQ);
@ -377,13 +349,13 @@ static struct gpio_k64_config gpio_k64_B_cfg = {
static struct gpio_k64_data gpio_data_B; static struct gpio_k64_data gpio_data_B;
DEVICE_INIT(gpio_k64_B, CONFIG_GPIO_K64_B_DEV_NAME, gpio_k64_B_init, DEVICE_INIT(gpio_k64_B, CONFIG_GPIO_K64_B_DEV_NAME, gpio_k64_B_init,
&gpio_data_B, &gpio_k64_B_cfg, &gpio_data_B, &gpio_k64_B_cfg,
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
static int gpio_k64_B_init(struct device *dev) static int gpio_k64_B_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_K64_PORTB_IRQ, CONFIG_GPIO_K64_PORTB_PRI, IRQ_CONNECT(CONFIG_GPIO_K64_PORTB_IRQ, CONFIG_GPIO_K64_PORTB_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_B), 0); gpio_k64_port_isr, DEVICE_GET(gpio_k64_B), 0);
irq_enable(CONFIG_GPIO_K64_PORTB_IRQ); irq_enable(CONFIG_GPIO_K64_PORTB_IRQ);
@ -405,13 +377,13 @@ static struct gpio_k64_config gpio_k64_C_cfg = {
static struct gpio_k64_data gpio_data_C; static struct gpio_k64_data gpio_data_C;
DEVICE_INIT(gpio_k64_C, CONFIG_GPIO_K64_C_DEV_NAME, gpio_k64_C_init, DEVICE_INIT(gpio_k64_C, CONFIG_GPIO_K64_C_DEV_NAME, gpio_k64_C_init,
&gpio_data_C, &gpio_k64_C_cfg, &gpio_data_C, &gpio_k64_C_cfg,
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
static int gpio_k64_C_init(struct device *dev) static int gpio_k64_C_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_K64_PORTC_IRQ, CONFIG_GPIO_K64_PORTC_PRI, IRQ_CONNECT(CONFIG_GPIO_K64_PORTC_IRQ, CONFIG_GPIO_K64_PORTC_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_C), 0); gpio_k64_port_isr, DEVICE_GET(gpio_k64_C), 0);
irq_enable(CONFIG_GPIO_K64_PORTC_IRQ); irq_enable(CONFIG_GPIO_K64_PORTC_IRQ);
@ -433,13 +405,13 @@ static struct gpio_k64_config gpio_k64_D_cfg = {
static struct gpio_k64_data gpio_data_D; static struct gpio_k64_data gpio_data_D;
DEVICE_INIT(gpio_k64_D, CONFIG_GPIO_K64_D_DEV_NAME, gpio_k64_D_init, DEVICE_INIT(gpio_k64_D, CONFIG_GPIO_K64_D_DEV_NAME, gpio_k64_D_init,
&gpio_data_D, &gpio_k64_D_cfg, &gpio_data_D, &gpio_k64_D_cfg,
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
static int gpio_k64_D_init(struct device *dev) static int gpio_k64_D_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_K64_PORTD_IRQ, CONFIG_GPIO_K64_PORTD_PRI, IRQ_CONNECT(CONFIG_GPIO_K64_PORTD_IRQ, CONFIG_GPIO_K64_PORTD_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_D), 0); gpio_k64_port_isr, DEVICE_GET(gpio_k64_D), 0);
irq_enable(CONFIG_GPIO_K64_PORTD_IRQ); irq_enable(CONFIG_GPIO_K64_PORTD_IRQ);
@ -461,13 +433,13 @@ static struct gpio_k64_config gpio_k64_E_cfg = {
static struct gpio_k64_data gpio_data_E; static struct gpio_k64_data gpio_data_E;
DEVICE_INIT(gpio_k64_E, CONFIG_GPIO_K64_E_DEV_NAME, gpio_k64_E_init, DEVICE_INIT(gpio_k64_E, CONFIG_GPIO_K64_E_DEV_NAME, gpio_k64_E_init,
&gpio_data_E, &gpio_k64_E_cfg, &gpio_data_E, &gpio_k64_E_cfg,
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
static int gpio_k64_E_init(struct device *dev) static int gpio_k64_E_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_K64_PORTE_IRQ, CONFIG_GPIO_K64_PORTE_PRI, IRQ_CONNECT(CONFIG_GPIO_K64_PORTE_IRQ, CONFIG_GPIO_K64_PORTE_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_E), 0); gpio_k64_port_isr, DEVICE_GET(gpio_k64_E), 0);
irq_enable(CONFIG_GPIO_K64_PORTE_IRQ); irq_enable(CONFIG_GPIO_K64_PORTE_IRQ);

13
drivers/gpio/gpio_k64.h
View file

@ -26,13 +26,12 @@
#include <gpio.h> #include <gpio.h>
/* GPIO Port Register offsets */ /* GPIO Port Register offsets */
#define GPIO_K64_DATA_OUT_OFFSET 0x00 /* Port Data Output */
#define GPIO_K64_DATA_OUT_OFFSET 0x00 /* Port Data Output Reg. offset */ #define GPIO_K64_SET_OUT_OFFSET 0x04 /* Port Set Output */
#define GPIO_K64_SET_OUT_OFFSET 0x04 /* Port Set Output Reg. offset */ #define GPIO_K64_CLR_OUT_OFFSET 0x08 /* Port Clear Output */
#define GPIO_K64_CLR_OUT_OFFSET 0x08 /* Port Clear Output Reg. offset */ #define GPIO_K64_TOGGLE_OUT_OFFSET 0x0C /* Port Toggle Output */
#define GPIO_K64_TOGGLE_OUT_OFFSET 0x0C /* Port Toggle Output Reg. offset */ #define GPIO_K64_DATA_IN_OFFSET 0x10 /* Port Data Input */
#define GPIO_K64_DATA_IN_OFFSET 0x10 /* Port Data Input Reg. offset */ #define GPIO_K64_DIR_OFFSET 0x14 /* Port Data Direction */
#define GPIO_K64_DIR_OFFSET 0x14 /* Port Data Direction Reg. offset */
/** Configuration data */ /** Configuration data */

25
drivers/gpio/gpio_mmio.c
View file

@ -102,8 +102,8 @@ static uint32_t _io_write(uint32_t addr, uint32_t bit, uint32_t value)
* *
* @return 0 if successful, failed otherwise * @return 0 if successful, failed otherwise
*/ */
static int gpio_mmio_config(struct device *dev, int access_op, static int gpio_mmio_config(struct device *dev,
uint32_t pin, int flags) int access_op, uint32_t pin, int flags)
{ {
const struct gpio_mmio_config * const cfg = const struct gpio_mmio_config * const cfg =
dev->config->config_info; dev->config->config_info;
@ -224,8 +224,8 @@ static int gpio_mmio_write(struct device *dev, int access_op,
* *
* @return 0 if successful, failed otherwise * @return 0 if successful, failed otherwise
*/ */
static int gpio_mmio_read(struct device *dev, int access_op, static int gpio_mmio_read(struct device *dev,
uint32_t pin, uint32_t *value) int access_op, uint32_t pin, uint32_t *value)
{ {
const struct gpio_mmio_config * const cfg = const struct gpio_mmio_config * const cfg =
dev->config->config_info; dev->config->config_info;
@ -237,7 +237,7 @@ static int gpio_mmio_read(struct device *dev, int access_op,
switch (access_op) { switch (access_op) {
case GPIO_ACCESS_BY_PIN: case GPIO_ACCESS_BY_PIN:
*value = cfg->access.read(cfg->reg.input, 0, 0); *value = cfg->access.read(cfg->reg.input, 0, 0);
*value &= (1 << pin) >> pin; *value &= BIT(pin) >> pin;
break; break;
case GPIO_ACCESS_BY_PORT: case GPIO_ACCESS_BY_PORT:
*value = cfg->access.read(cfg->reg.input, 0, 0); *value = cfg->access.read(cfg->reg.input, 0, 0);
@ -249,8 +249,7 @@ static int gpio_mmio_read(struct device *dev, int access_op,
return 0; return 0;
} }
static int gpio_mmio_set_callback(struct device *dev, static int gpio_mmio_set_callback(struct device *dev, gpio_callback_t callback)
gpio_callback_t callback)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
ARG_UNUSED(callback); ARG_UNUSED(callback);
@ -259,7 +258,7 @@ static int gpio_mmio_set_callback(struct device *dev,
} }
static int gpio_mmio_enable_callback(struct device *dev, static int gpio_mmio_enable_callback(struct device *dev,
int access_op, uint32_t pin) int access_op, uint32_t pin)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
ARG_UNUSED(access_op); ARG_UNUSED(access_op);
@ -269,7 +268,7 @@ static int gpio_mmio_enable_callback(struct device *dev,
} }
static int gpio_mmio_disable_callback(struct device *dev, static int gpio_mmio_disable_callback(struct device *dev,
int access_op, uint32_t pin) int access_op, uint32_t pin)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
ARG_UNUSED(access_op); ARG_UNUSED(access_op);
@ -341,8 +340,8 @@ static struct gpio_mmio_config gpio_mmio_0_cfg = {
}; };
DEVICE_INIT(gpio_mmio_0, CONFIG_GPIO_MMIO_0_DEV_NAME, gpio_mmio_init, DEVICE_INIT(gpio_mmio_0, CONFIG_GPIO_MMIO_0_DEV_NAME, gpio_mmio_init,
(void *)0, &gpio_mmio_0_cfg, NULL, &gpio_mmio_0_cfg,
SECONDARY, CONFIG_GPIO_MMIO_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_MMIO_INIT_PRIORITY);
#endif /* CONFIG_GPIO_MMIO_0 */ #endif /* CONFIG_GPIO_MMIO_0 */
@ -371,7 +370,7 @@ static struct gpio_mmio_config gpio_mmio_1_cfg = {
}; };
DEVICE_INIT(gpio_mmio_1, CONFIG_GPIO_MMIO_1_DEV_NAME, gpio_mmio_init, DEVICE_INIT(gpio_mmio_1, CONFIG_GPIO_MMIO_1_DEV_NAME, gpio_mmio_init,
(void *)0, &gpio_mmio_1_cfg, NULL, &gpio_mmio_1_cfg,
SECONDARY, CONFIG_GPIO_MMIO_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_MMIO_INIT_PRIORITY);
#endif /* CONFIG_GPIO_MMIO_1 */ #endif /* CONFIG_GPIO_MMIO_1 */

12
drivers/gpio/gpio_mmio.h
View file

@ -33,17 +33,17 @@ extern "C" {
* NORMAL: 0 - disable, 1 - enable * NORMAL: 0 - disable, 1 - enable
* INV: 0 - enable, 1 - disable * INV: 0 - enable, 1 - disable
*/ */
#define GPIO_MMIO_CFG_EN_NORMAL (0 << 0) #define GPIO_MMIO_CFG_EN_NORMAL (0)
#define GPIO_MMIO_CFG_EN_INV (1 << 0) #define GPIO_MMIO_CFG_EN_INV BIT(0)
#define GPIO_MMIO_CFG_EN_MASK (1 << 0) #define GPIO_MMIO_CFG_EN_MASK BIT(0)
/* For direction register: /* For direction register:
* NORMAL: 0 - pin is output, 1 - pin is input * NORMAL: 0 - pin is output, 1 - pin is input
* INV: 0 - pin is input, 1 - pin is output * INV: 0 - pin is input, 1 - pin is output
*/ */
#define GPIO_MMIO_CFG_DIR_NORMAL (0 << 1) #define GPIO_MMIO_CFG_DIR_NORMAL (0)
#define GPIO_MMIO_CFG_DIR_INV (1 << 1) #define GPIO_MMIO_CFG_DIR_INV BIT(1)
#define GPIO_MMIO_CFG_DIR_MASK (1 << 1) #define GPIO_MMIO_CFG_DIR_MASK BIT(1)
/** /**
* @brief Initialization function for GPIO driver * @brief Initialization function for GPIO driver

32
drivers/gpio/gpio_pcal9535a.c
View file

@ -22,6 +22,7 @@
#include <nanokernel.h> #include <nanokernel.h>
#include <misc/util.h>
#include <gpio.h> #include <gpio.h>
#include <i2c.h> #include <i2c.h>
@ -330,11 +331,11 @@ static int _setup_pin_polarity(struct device *dev, int access_op,
switch (access_op) { switch (access_op) {
case GPIO_ACCESS_BY_PIN: case GPIO_ACCESS_BY_PIN:
bit_mask = 1 << pin; bit_mask = BIT(pin);
/* normal == 0, invert == 1 */ /* normal == 0, invert == 1 */
if ((flags & GPIO_POL_MASK) == GPIO_POL_INV) { if ((flags & GPIO_POL_MASK) == GPIO_POL_INV) {
new_value = 1 << pin; new_value = BIT(pin);
} }
port->all &= ~bit_mask; port->all &= ~bit_mask;
@ -440,7 +441,7 @@ static int gpio_pcal9535a_write(struct device *dev, int access_op,
/* Invert input value for pins configurated as active low. */ /* Invert input value for pins configurated as active low. */
switch (access_op) { switch (access_op) {
case GPIO_ACCESS_BY_PIN: case GPIO_ACCESS_BY_PIN:
bit_mask = 1 << pin; bit_mask = BIT(pin);
new_value = (value << pin) & bit_mask; new_value = (value << pin) & bit_mask;
new_value ^= (drv_data->out_pol_inv & bit_mask); new_value ^= (drv_data->out_pol_inv & bit_mask);
@ -621,9 +622,9 @@ static struct gpio_pcal9535a_drv_data gpio_pcal9535a_0_drvdata = {
/* This has to init after I2C master */ /* This has to init after I2C master */
DEVICE_INIT(gpio_pcal9535a_0, CONFIG_GPIO_PCAL9535A_0_DEV_NAME, DEVICE_INIT(gpio_pcal9535a_0, CONFIG_GPIO_PCAL9535A_0_DEV_NAME,
gpio_pcal9535a_init, gpio_pcal9535a_init,
&gpio_pcal9535a_0_drvdata, &gpio_pcal9535a_0_cfg, &gpio_pcal9535a_0_drvdata, &gpio_pcal9535a_0_cfg,
SECONDARY, CONFIG_GPIO_PCAL9535A_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_PCAL9535A_INIT_PRIORITY);
#endif /* CONFIG_GPIO_PCAL9535A_0 */ #endif /* CONFIG_GPIO_PCAL9535A_0 */
@ -648,9 +649,9 @@ static struct gpio_pcal9535a_drv_data gpio_pcal9535a_1_drvdata = {
/* This has to init after I2C master */ /* This has to init after I2C master */
DEVICE_INIT(gpio_pcal9535a_1, CONFIG_GPIO_PCAL9535A_1_DEV_NAME, DEVICE_INIT(gpio_pcal9535a_1, CONFIG_GPIO_PCAL9535A_1_DEV_NAME,
gpio_pcal9535a_init, gpio_pcal9535a_init,
&gpio_pcal9535a_1_drvdata, &gpio_pcal9535a_1_cfg, &gpio_pcal9535a_1_drvdata, &gpio_pcal9535a_1_cfg,
SECONDARY, CONFIG_GPIO_PCAL9535A_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_PCAL9535A_INIT_PRIORITY);
#endif /* CONFIG_GPIO_PCAL9535A_1 */ #endif /* CONFIG_GPIO_PCAL9535A_1 */
@ -675,9 +676,9 @@ static struct gpio_pcal9535a_drv_data gpio_pcal9535a_2_drvdata = {
/* This has to init after I2C master */ /* This has to init after I2C master */
DEVICE_INIT(gpio_pcal9535a_2, CONFIG_GPIO_PCAL9535A_2_DEV_NAME, DEVICE_INIT(gpio_pcal9535a_2, CONFIG_GPIO_PCAL9535A_2_DEV_NAME,
gpio_pcal9535a_init, gpio_pcal9535a_init,
&gpio_pcal9535a_2_drvdata, &gpio_pcal9535a_2_cfg, &gpio_pcal9535a_2_drvdata, &gpio_pcal9535a_2_cfg,
SECONDARY, CONFIG_GPIO_PCAL9535A_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_PCAL9535A_INIT_PRIORITY);
#endif /* CONFIG_GPIO_PCAL9535A_2 */ #endif /* CONFIG_GPIO_PCAL9535A_2 */
@ -702,9 +703,8 @@ static struct gpio_pcal9535a_drv_data gpio_pcal9535a_3_drvdata = {
/* This has to init after I2C master */ /* This has to init after I2C master */
DEVICE_INIT(gpio_pcal9535a_3, CONFIG_GPIO_PCAL9535A_3_DEV_NAME, DEVICE_INIT(gpio_pcal9535a_3, CONFIG_GPIO_PCAL9535A_3_DEV_NAME,
gpio_pcal9535a_init, gpio_pcal9535a_init,
&gpio_pcal9535a_3_drvdata, &gpio_pcal9535a_3_cfg, &gpio_pcal9535a_3_drvdata, &gpio_pcal9535a_3_cfg,
SECONDARY, CONFIG_GPIO_PCAL9535A_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_PCAL9535A_INIT_PRIORITY);
#endif /* CONFIG_GPIO_PCAL9535A_3 */ #endif /* CONFIG_GPIO_PCAL9535A_3 */

41
drivers/gpio/gpio_qmsi.c
View file

@ -79,19 +79,21 @@ static void gpio_qmsi_callback(struct device *port, uint32_t status)
const uint32_t enabled_mask = context->pin_callbacks & status; const uint32_t enabled_mask = context->pin_callbacks & status;
int bit; int bit;
if (!context->callback) if (!context->callback) {
return; return;
}
if (context->port_callback) { if (context->port_callback) {
context->callback(port, status); context->callback(port, status);
return; return;
} }
if (!enabled_mask) if (!enabled_mask) {
return; return;
}
for (bit = 0; bit < config->num_pins; bit++) { for (bit = 0; bit < config->num_pins; bit++) {
if (enabled_mask & (1 << bit)) { if (enabled_mask & BIT(bit)) {
context->callback(port, bit); context->callback(port, bit);
} }
} }
@ -143,9 +145,12 @@ static inline void qmsi_pin_config(struct device *port, uint32_t pin, int flags)
if (flags & GPIO_INT) { if (flags & GPIO_INT) {
qmsi_write_bit(&cfg.int_type, pin, (flags & GPIO_INT_EDGE)); qmsi_write_bit(&cfg.int_type, pin, (flags & GPIO_INT_EDGE));
qmsi_write_bit(&cfg.int_polarity, pin, (flags & GPIO_INT_ACTIVE_HIGH)); qmsi_write_bit(&cfg.int_polarity, pin,
qmsi_write_bit(&cfg.int_debounce, pin, (flags & GPIO_INT_DEBOUNCE)); (flags & GPIO_INT_ACTIVE_HIGH));
qmsi_write_bit(&cfg.int_bothedge, pin, (flags & GPIO_INT_DOUBLE_EDGE)); qmsi_write_bit(&cfg.int_debounce, pin,
(flags & GPIO_INT_DEBOUNCE));
qmsi_write_bit(&cfg.int_bothedge, pin,
(flags & GPIO_INT_DOUBLE_EDGE));
qmsi_write_bit(&cfg.int_en, pin, 1); qmsi_write_bit(&cfg.int_en, pin, 1);
} }
@ -178,8 +183,8 @@ static inline void qmsi_port_config(struct device *port, int flags)
} }
} }
static inline int gpio_qmsi_config(struct device *port, int access_op, static inline int gpio_qmsi_config(struct device *port,
uint32_t pin, int flags) int access_op, uint32_t pin, int flags)
{ {
if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) || if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) { ((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
@ -194,8 +199,8 @@ static inline int gpio_qmsi_config(struct device *port, int access_op,
return 0; return 0;
} }
static inline int gpio_qmsi_write(struct device *port, int access_op, static inline int gpio_qmsi_write(struct device *port,
uint32_t pin, uint32_t value) int access_op, uint32_t pin, uint32_t value)
{ {
struct gpio_qmsi_config *gpio_config = port->config->config_info; struct gpio_qmsi_config *gpio_config = port->config->config_info;
qm_gpio_t gpio = gpio_config->gpio; qm_gpio_t gpio = gpio_config->gpio;
@ -213,8 +218,8 @@ static inline int gpio_qmsi_write(struct device *port, int access_op,
return 0; return 0;
} }
static inline int gpio_qmsi_read(struct device *port, int access_op, static inline int gpio_qmsi_read(struct device *port,
uint32_t pin, uint32_t *value) int access_op, uint32_t pin, uint32_t *value)
{ {
struct gpio_qmsi_config *gpio_config = port->config->config_info; struct gpio_qmsi_config *gpio_config = port->config->config_info;
qm_gpio_t gpio = gpio_config->gpio; qm_gpio_t gpio = gpio_config->gpio;
@ -229,7 +234,7 @@ static inline int gpio_qmsi_read(struct device *port, int access_op,
} }
static inline int gpio_qmsi_set_callback(struct device *port, static inline int gpio_qmsi_set_callback(struct device *port,
gpio_callback_t callback) gpio_callback_t callback)
{ {
struct gpio_qmsi_runtime *context = port->driver_data; struct gpio_qmsi_runtime *context = port->driver_data;
@ -238,8 +243,8 @@ static inline int gpio_qmsi_set_callback(struct device *port,
return 0; return 0;
} }
static inline int gpio_qmsi_enable_callback(struct device *port, int access_op, static inline int gpio_qmsi_enable_callback(struct device *port,
uint32_t pin) int access_op, uint32_t pin)
{ {
struct gpio_qmsi_runtime *context = port->driver_data; struct gpio_qmsi_runtime *context = port->driver_data;
@ -252,8 +257,8 @@ static inline int gpio_qmsi_enable_callback(struct device *port, int access_op,
return 0; return 0;
} }
static inline int gpio_qmsi_disable_callback(struct device *port, int access_op, static inline int gpio_qmsi_disable_callback(struct device *port,
uint32_t pin) int access_op, uint32_t pin)
{ {
struct gpio_qmsi_runtime *context = port->driver_data; struct gpio_qmsi_runtime *context = port->driver_data;
@ -303,7 +308,6 @@ int gpio_qmsi_init(struct device *port)
irq_enable(CONFIG_GPIO_QMSI_0_IRQ); irq_enable(CONFIG_GPIO_QMSI_0_IRQ);
QM_SCSS_INT->int_gpio_mask &= ~BIT(0); QM_SCSS_INT->int_gpio_mask &= ~BIT(0);
break; break;
#ifdef CONFIG_GPIO_QMSI_AON #ifdef CONFIG_GPIO_QMSI_AON
case QM_AON_GPIO_0: case QM_AON_GPIO_0:
IRQ_CONNECT(CONFIG_GPIO_QMSI_AON_IRQ, IRQ_CONNECT(CONFIG_GPIO_QMSI_AON_IRQ,
@ -313,7 +317,6 @@ int gpio_qmsi_init(struct device *port)
QM_SCSS_INT->int_aon_gpio_mask &= ~BIT(0); QM_SCSS_INT->int_aon_gpio_mask &= ~BIT(0);
break; break;
#endif /* CONFIG_GPIO_QMSI_AON */ #endif /* CONFIG_GPIO_QMSI_AON */
default: default:
return -EIO; return -EIO;
} }

24
drivers/gpio/gpio_sch.c
View file

@ -97,8 +97,7 @@ static inline void _set_data_reg(uint32_t *reg, uint8_t pin, uint8_t set)
*reg |= (set << pin) & BIT(pin); *reg |= (set << pin) & BIT(pin);
} }
static void _gpio_pin_config(struct device *dev, static void _gpio_pin_config(struct device *dev, uint32_t pin, int flags)
uint32_t pin, int flags)
{ {
struct gpio_sch_config *info = dev->config->config_info; struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data; struct gpio_sch_data *gpio = dev->driver_data;
@ -116,7 +115,7 @@ static void _gpio_pin_config(struct device *dev,
} }
DBG("Setting up pin %d to active_high %d and active_low %d\n", DBG("Setting up pin %d to active_high %d and active_low %d\n",
active_high, active_low); active_high, active_low);
} }
/* We store the gtpe/gtne settings. These will be used once /* We store the gtpe/gtne settings. These will be used once
@ -137,7 +136,7 @@ static inline void _gpio_port_config(struct device *dev, int flags)
} }
static int gpio_sch_config(struct device *dev, static int gpio_sch_config(struct device *dev,
int access_op, uint32_t pin, int flags) int access_op, uint32_t pin, int flags)
{ {
struct gpio_sch_config *info = dev->config->config_info; struct gpio_sch_config *info = dev->config->config_info;
@ -155,7 +154,7 @@ static int gpio_sch_config(struct device *dev,
} }
static int gpio_sch_write(struct device *dev, static int gpio_sch_write(struct device *dev,
int access_op, uint32_t pin, uint32_t value) int access_op, uint32_t pin, uint32_t value)
{ {
struct gpio_sch_config *info = dev->config->config_info; struct gpio_sch_config *info = dev->config->config_info;
@ -240,8 +239,7 @@ loop:
} }
} }
static int gpio_sch_set_callback(struct device *dev, static int gpio_sch_set_callback(struct device *dev, gpio_callback_t callback)
gpio_callback_t callback)
{ {
struct gpio_sch_data *gpio = dev->driver_data; struct gpio_sch_data *gpio = dev->driver_data;
@ -265,7 +263,7 @@ static int gpio_sch_set_callback(struct device *dev,
} }
static int gpio_sch_enable_callback(struct device *dev, static int gpio_sch_enable_callback(struct device *dev,
int access_op, uint32_t pin) int access_op, uint32_t pin)
{ {
struct gpio_sch_config *info = dev->config->config_info; struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data; struct gpio_sch_data *gpio = dev->driver_data;
@ -293,7 +291,7 @@ static int gpio_sch_enable_callback(struct device *dev,
} }
static int gpio_sch_disable_callback(struct device *dev, static int gpio_sch_disable_callback(struct device *dev,
int access_op, uint32_t pin) int access_op, uint32_t pin)
{ {
struct gpio_sch_config *info = dev->config->config_info; struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data; struct gpio_sch_data *gpio = dev->driver_data;
@ -362,8 +360,8 @@ struct gpio_sch_config gpio_sch_0_config = {
struct gpio_sch_data gpio_data_0; struct gpio_sch_data gpio_data_0;
DEVICE_INIT(gpio_0, CONFIG_GPIO_SCH_0_DEV_NAME, gpio_sch_init, DEVICE_INIT(gpio_0, CONFIG_GPIO_SCH_0_DEV_NAME, gpio_sch_init,
&gpio_data_0, &gpio_sch_0_config, &gpio_data_0, &gpio_sch_0_config,
SECONDARY, CONFIG_GPIO_SCH_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_SCH_INIT_PRIORITY);
#endif /* CONFIG_GPIO_SCH_0 */ #endif /* CONFIG_GPIO_SCH_0 */
#if CONFIG_GPIO_SCH_1 #if CONFIG_GPIO_SCH_1
@ -376,7 +374,7 @@ struct gpio_sch_config gpio_sch_1_config = {
struct gpio_sch_data gpio_data_1; struct gpio_sch_data gpio_data_1;
DEVICE_INIT(gpio_1, CONFIG_GPIO_SCH_1_DEV_NAME, gpio_sch_init, DEVICE_INIT(gpio_1, CONFIG_GPIO_SCH_1_DEV_NAME, gpio_sch_init,
&gpio_data_1, &gpio_sch_1_config, &gpio_data_1, &gpio_sch_1_config,
SECONDARY, CONFIG_GPIO_SCH_INIT_PRIORITY); SECONDARY, CONFIG_GPIO_SCH_INIT_PRIORITY);
#endif /* CONFIG_GPIO_SCH_1 */ #endif /* CONFIG_GPIO_SCH_1 */

24
drivers/gpio/gpio_stm32.c
View file

@ -45,7 +45,7 @@ static void gpio_stm32_isr(int line, void *arg)
return; return;
} }
is_enabled = data->enabled_mask & (1 << line); is_enabled = data->enabled_mask & BIT(line);
if (!is_enabled) { if (!is_enabled) {
return; return;
@ -91,12 +91,14 @@ static int gpio_stm32_config(struct device *dev, int access_op,
int edge = 0; int edge = 0;
if (flags & GPIO_INT_DOUBLE_EDGE) { if (flags & GPIO_INT_DOUBLE_EDGE) {
edge = STM32_EXTI_TRIG_RISING | STM32_EXTI_TRIG_FALLING; edge = STM32_EXTI_TRIG_RISING |
STM32_EXTI_TRIG_FALLING;
} else if (flags & GPIO_INT_ACTIVE_HIGH) { } else if (flags & GPIO_INT_ACTIVE_HIGH) {
edge = STM32_EXTI_TRIG_RISING; edge = STM32_EXTI_TRIG_RISING;
} else { } else {
edge = STM32_EXTI_TRIG_FALLING; edge = STM32_EXTI_TRIG_FALLING;
} }
stm32_exti_trigger(exti, pin, edge); stm32_exti_trigger(exti, pin, edge);
} }
@ -110,7 +112,7 @@ static int gpio_stm32_config(struct device *dev, int access_op,
* @brief Set the pin or port output * @brief Set the pin or port output
*/ */
static int gpio_stm32_write(struct device *dev, int access_op, static int gpio_stm32_write(struct device *dev, int access_op,
uint32_t pin, uint32_t value) uint32_t pin, uint32_t value)
{ {
struct gpio_stm32_config *cfg = dev->config->config_info; struct gpio_stm32_config *cfg = dev->config->config_info;
@ -157,7 +159,7 @@ static int gpio_stm32_enable_callback(struct device *dev,
return -ENOTSUP; return -ENOTSUP;
} }
data->enabled_mask |= 1 << pin; data->enabled_mask |= BIT(pin);
return 0; return 0;
} }
@ -171,7 +173,7 @@ static int gpio_stm32_disable_callback(struct device *dev,
return -ENOTSUP; return -ENOTSUP;
} }
data->enabled_mask &= ~(1 << pin); data->enabled_mask &= ~BIT(pin);
return 0; return 0;
} }
@ -235,12 +237,12 @@ static struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
}; \ }; \
static struct gpio_stm32_data gpio_stm32_data_## __suffix; \ static struct gpio_stm32_data gpio_stm32_data_## __suffix; \
DEVICE_INIT(gpio_stm32_## __suffix, \ DEVICE_INIT(gpio_stm32_## __suffix, \
__name, \ __name, \
gpio_stm32_init, \ gpio_stm32_init, \
&gpio_stm32_data_## __suffix, \ &gpio_stm32_data_## __suffix, \
&gpio_stm32_cfg_## __suffix, \ &gpio_stm32_cfg_## __suffix, \
SECONDARY, \ SECONDARY, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE) CONFIG_KERNEL_INIT_PRIORITY_DEVICE)
#ifdef CONFIG_GPIO_STM32_PORTA #ifdef CONFIG_GPIO_STM32_PORTA
GPIO_DEVICE_INIT("GPIOA", a, GPIOA_BASE, STM32_PORTA, GPIO_DEVICE_INIT("GPIOA", a, GPIOA_BASE, STM32_PORTA,