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soc: intel_s1000: add audio master clock config

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Added a SOC level routine to configure master clock outputs
if CONFIG_AUDIO is defined.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
This commit is contained in:
Sathish Kuttan 2019-02-10 20:57:09 -08:00 • committed by Anas Nashif
commit 66d0898a21
2 changed files with 33 additions and 1 deletions
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19
soc/xtensa/intel_s1000/soc.c
View file

@ -184,6 +184,24 @@ u32_t soc_get_ref_clk_freq(void)
return ref_clk_freq; return ref_clk_freq;
} }
static inline void soc_set_audio_mclk(void)
{
#if (CONFIG_AUDIO)
int mclk;
volatile struct soc_mclk_control_regs *mclk_regs =
(volatile struct soc_mclk_control_regs *)SOC_MCLK_DIV_CTRL_BASE;
for (mclk = 0; mclk < SOC_NUM_MCLK_OUTPUTS; mclk++) {
/*
* set divider to bypass mode which makes MCLK output frequency
* to be the same as referece clock frequency
*/
mclk_regs->mdivxr[mclk] = SOC_MDIVXR_SET_DIVIDER_BYPASS;
mclk_regs->mdivctrl |= SOC_MDIVCTRL_MCLK_OUT_EN(mclk);
}
#endif
}
static inline void soc_set_dmic_power(void) static inline void soc_set_dmic_power(void)
{ {
#if (CONFIG_AUDIO_INTEL_DMIC) #if (CONFIG_AUDIO_INTEL_DMIC)
@ -228,6 +246,7 @@ static inline void soc_set_power_and_clock(void)
soc_set_dmic_power(); soc_set_dmic_power();
soc_set_gna_power(); soc_set_gna_power();
soc_set_audio_mclk();
} }
static inline void soc_read_bootstraps(void) static inline void soc_read_bootstraps(void)

15
soc/xtensa/intel_s1000/soc.h
View file

@ -99,7 +99,20 @@
#define SSP_SIZE 0x0000200 #define SSP_SIZE 0x0000200
#define SSP_BASE(x) (0x00077000 + (x) * SSP_SIZE) #define SSP_BASE(x) (0x00077000 + (x) * SSP_SIZE)
#define SSP_MN_DIV_SIZE (8) #define SSP_MN_DIV_SIZE (8)
#define SSP_MN_DIV_BASE(x) (0x00078D00 + ((x) * SSP_MN_DIV_SIZE)) #define SSP_MN_DIV_BASE(x) \
(0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
/* MCLK control */
#define SOC_MCLK_DIV_CTRL_BASE 0x78C00
#define SOC_NUM_MCLK_OUTPUTS 2
#define SOC_MDIVCTRL_MCLK_OUT_EN(mclk) BIT(mclk)
#define SOC_MDIVXR_SET_DIVIDER_BYPASS BIT_MASK(12)
struct soc_mclk_control_regs {
u32_t mdivctrl;
u32_t reserved[31];
u32_t mdivxr[SOC_NUM_MCLK_OUTPUTS];
};
#define PDM_BASE 0x00010000 #define PDM_BASE 0x00010000