xtensa: cleanup Kconfig file
* Wording on CONFIG_SIMULATOR_XTENSA * Remove "default n" as default is no anyway. * Remove some tabs as we almost never indent inside a if block in Zephyr. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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1 changed files with 40 additions and 42 deletions
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@ -10,9 +10,9 @@ config ARCH
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default "xtensa"
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config SIMULATOR_XTENSA
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bool "Simulator Configuration"
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bool "Simulator Target"
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help
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Specify if the board configuration should be treated as a simulator.
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Enable if building to run on simulator.
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config XTENSA_RESET_VECTOR
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bool "Build reset vector code"
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@ -97,7 +97,6 @@ if CPU_HAS_MMU
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config XTENSA_MMU
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bool "Xtensa MMU Support"
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default n
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select MMU
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select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
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select XTENSA_SMALL_VECTOR_TABLE_ENTRY
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@ -108,52 +107,51 @@ config XTENSA_MMU
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if XTENSA_MMU
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choice
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prompt "PageTable virtual adddress"
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default XTENSA_MMU_PTEVADDR_20000000
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help
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The virtual address for Xtensa page table (PTEVADDR).
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choice
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prompt "PageTable virtual address"
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default XTENSA_MMU_PTEVADDR_20000000
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help
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The virtual address for Xtensa page table (PTEVADDR).
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config XTENSA_MMU_PTEVADDR_20000000
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bool "0x20000000"
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config XTENSA_MMU_PTEVADDR_20000000
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bool "0x20000000"
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endchoice
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endchoice
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config XTENSA_MMU_PTEVADDR
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hex
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default 0x20000000 if XTENSA_MMU_PTEVADDR_20000000
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help
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The virtual address for Xtensa page table (PTEVADDR).
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config XTENSA_MMU_PTEVADDR
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hex
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default 0x20000000 if XTENSA_MMU_PTEVADDR_20000000
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help
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The virtual address for Xtensa page table (PTEVADDR).
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config XTENSA_MMU_PTEVADDR_SHIFT
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int
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default 29 if XTENSA_MMU_PTEVADDR_20000000
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help
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The bit shift number for the virtual address for Xtensa
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page table (PTEVADDR).
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config XTENSA_MMU_PTEVADDR_SHIFT
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int
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default 29 if XTENSA_MMU_PTEVADDR_20000000
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help
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The bit shift number for the virtual address for Xtensa
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page table (PTEVADDR).
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config XTENSA_MMU_NUM_L1_TABLES
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int "Number of L1 page tables"
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default 1 if !USERSPACE
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default 4
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help
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This option specifies the maximum number of traslation tables.
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Translation tables are directly related to the number of
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memory domains in the target, considering the kernel itself requires one.
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config XTENSA_MMU_NUM_L1_TABLES
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int "Number of L1 page tables"
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default 1 if !USERSPACE
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default 4
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help
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This option specifies the maximum number of traslation tables.
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Translation tables are directly related to the number of
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memory domains in the target, considering the kernel itself requires one.
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config XTENSA_MMU_NUM_L2_TABLES
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int "Number of L2 page tables"
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default 20 if USERSPACE
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default 10
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help
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Each table can address up to 4MB memory address.
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config XTENSA_MMU_NUM_L2_TABLES
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int "Number of L2 page tables"
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default 20 if USERSPACE
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default 10
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help
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Each table can address up to 4MB memory address.
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config XTENSA_MMU_DOUBLE_MAP
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bool "Map memory in cached and uncached region"
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default n
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help
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This option specifies that the memory is mapped in two
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distinct region, cached and uncached.
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config XTENSA_MMU_DOUBLE_MAP
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bool "Map memory in cached and uncached region"
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help
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This option specifies that the memory is mapped in two
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distinct region, cached and uncached.
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endif # XTENSA_MMU
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