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xtensa: cleanup Kconfig file

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* Wording on CONFIG_SIMULATOR_XTENSA
* Remove "default n" as default is no anyway.
* Remove some tabs as we almost never indent inside a if block
  in Zephyr.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2023-12-06 11:33:11 -08:00 • committed by Carles Cufí
commit 6694390ac8
1 changed files with 40 additions and 42 deletions
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82
arch/xtensa/Kconfig
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@ -10,9 +10,9 @@ config ARCH
default "xtensa"
config SIMULATOR_XTENSA
bool "Simulator Configuration"
bool "Simulator Target"
help
Specify if the board configuration should be treated as a simulator.
Enable if building to run on simulator.
config XTENSA_RESET_VECTOR
bool "Build reset vector code"
@ -97,7 +97,6 @@ if CPU_HAS_MMU
config XTENSA_MMU
bool "Xtensa MMU Support"
default n
select MMU
select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
select XTENSA_SMALL_VECTOR_TABLE_ENTRY
@ -108,52 +107,51 @@ config XTENSA_MMU
if XTENSA_MMU
choice
prompt "PageTable virtual adddress"
default XTENSA_MMU_PTEVADDR_20000000
help
The virtual address for Xtensa page table (PTEVADDR).
choice
prompt "PageTable virtual address"
default XTENSA_MMU_PTEVADDR_20000000
help
The virtual address for Xtensa page table (PTEVADDR).
config XTENSA_MMU_PTEVADDR_20000000
bool "0x20000000"
config XTENSA_MMU_PTEVADDR_20000000
bool "0x20000000"
endchoice
endchoice
config XTENSA_MMU_PTEVADDR
hex
default 0x20000000 if XTENSA_MMU_PTEVADDR_20000000
help
The virtual address for Xtensa page table (PTEVADDR).
config XTENSA_MMU_PTEVADDR
hex
default 0x20000000 if XTENSA_MMU_PTEVADDR_20000000
help
The virtual address for Xtensa page table (PTEVADDR).
config XTENSA_MMU_PTEVADDR_SHIFT
int
default 29 if XTENSA_MMU_PTEVADDR_20000000
help
The bit shift number for the virtual address for Xtensa
page table (PTEVADDR).
config XTENSA_MMU_PTEVADDR_SHIFT
int
default 29 if XTENSA_MMU_PTEVADDR_20000000
help
The bit shift number for the virtual address for Xtensa
page table (PTEVADDR).
config XTENSA_MMU_NUM_L1_TABLES
int "Number of L1 page tables"
default 1 if !USERSPACE
default 4
help
This option specifies the maximum number of traslation tables.
Translation tables are directly related to the number of
memory domains in the target, considering the kernel itself requires one.
config XTENSA_MMU_NUM_L1_TABLES
int "Number of L1 page tables"
default 1 if !USERSPACE
default 4
help
This option specifies the maximum number of traslation tables.
Translation tables are directly related to the number of
memory domains in the target, considering the kernel itself requires one.
config XTENSA_MMU_NUM_L2_TABLES
int "Number of L2 page tables"
default 20 if USERSPACE
default 10
help
Each table can address up to 4MB memory address.
config XTENSA_MMU_NUM_L2_TABLES
int "Number of L2 page tables"
default 20 if USERSPACE
default 10
help
Each table can address up to 4MB memory address.
config XTENSA_MMU_DOUBLE_MAP
bool "Map memory in cached and uncached region"
default n
help
This option specifies that the memory is mapped in two
distinct region, cached and uncached.
config XTENSA_MMU_DOUBLE_MAP
bool "Map memory in cached and uncached region"
help
This option specifies that the memory is mapped in two
distinct region, cached and uncached.
endif # XTENSA_MMU