diff --git a/dts/arm/nxp/nxp_s32k344_m7.dtsi b/dts/arm/nxp/nxp_s32k344_m7.dtsi
index 91628a3dad4..a98c379bb42 100644
--- a/dts/arm/nxp/nxp_s32k344_m7.dtsi
+++ b/dts/arm/nxp/nxp_s32k344_m7.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023-2024 NXP
+ * Copyright 2023-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 #include <mem.h>
 #include <zephyr/dt-bindings/clock/nxp_s32k344_clock.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
 
 / {
 	cpus {
@@ -45,12 +46,14 @@
 			compatible = "zephyr,memory-region", "arm,itcm";
 			reg = <0x00000000 DT_SIZE_K(64)>;
 			zephyr,memory-region = "ITCM";
+			zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>;
 		};
 
 		dtcm: memory@20000000 {
 			compatible = "zephyr,memory-region", "arm,dtcm";
 			reg = <0x20000000 DT_SIZE_K(128)>;
 			zephyr,memory-region = "DTCM";
+			zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
 		};
 
 		sram0_1: sram0_1@20400000 {
diff --git a/soc/nxp/s32/s32k3/mpu_regions.c b/soc/nxp/s32/s32k3/mpu_regions.c
index ce6e5fcfd20..a410948f1b2 100644
--- a/soc/nxp/s32/s32k3/mpu_regions.c
+++ b/soc/nxp/s32/s32k3/mpu_regions.c
@@ -12,11 +12,16 @@
 extern char _rom_attr[];
 #endif
 
+#define REGION_PERIPHERAL_BASE_ADDRESS 0x40000000
+#define REGION_PERIPHERAL_SIZE         REGION_512M
+#define REGION_PPB_BASE_ADDRESS        0xE0000000
+#define REGION_PPB_SIZE                REGION_1M
+
 static struct arm_mpu_region mpu_regions[] = {
 
 	/* ERR011573: use first region to prevent speculative access in entire memory space */
 	{
-		.name = "BACKGROUND",
+		.name = "UNMAPPED",
 		.base = 0,
 		.attr = {REGION_4G | MPU_RASR_XN_Msk | P_NA_U_NA_Msk},
 	},
@@ -42,6 +47,18 @@ static struct arm_mpu_region mpu_regions[] = {
 		.attr = {(uint32_t)_rom_attr},
 	},
 #endif
+
+	{
+		.name = "PERIPHERALS",
+		.base = REGION_PERIPHERAL_BASE_ADDRESS,
+		.attr = REGION_IO_ATTR(REGION_PERIPHERAL_SIZE),
+	},
+
+	{
+		.name = "PPB",
+		.base = REGION_PPB_BASE_ADDRESS,
+		.attr = REGION_PPB_ATTR(REGION_PPB_SIZE),
+	},
 };
 
 const struct arm_mpu_config mpu_config = {