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soc: xtensa: esp32s2: add data cache initialization

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during esp32s2 boot.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
This commit is contained in:
Glauber Maroto Ferreira 2021-11-08 17:18:31 -03:00 • committed by Anas Nashif
commit 661b5cf84d
3 changed files with 61 additions and 0 deletions
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12
soc/xtensa/esp32s2/Kconfig.soc
View file

@ -58,6 +58,18 @@ choice
endchoice
choice
prompt "Data cache line size"
default ESP32S2_DATA_CACHE_LINE_32B
config ESP32S2_DATA_CACHE_LINE_16B
bool "16 Bytes"
config ESP32S2_DATA_CACHE_LINE_32B
bool "32 Bytes"
endchoice
config ESP32S2_INSTRUCTION_CACHE_SIZE
hex
default 0x4000 if ESP32S2_INSTRUCTION_CACHE_16KB

39
soc/xtensa/esp32s2/soc.c
View file

@ -80,6 +80,45 @@ void __attribute__((section(".iram1"))) __start(void)
esp_rom_Cache_Invalidate_ICache_All();
esp_rom_Cache_Resume_ICache(0);
/*
* If we need use SPIRAM, we should use data cache, or if we want to
* access rodata, we also should use data cache.
* Configure the mode of data : cache size, cache associated ways, cache
* line size.
* Enable data cache, so if we don't use SPIRAM, it just works.
*/
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
#if CONFIG_ESP32S2_DATA_CACHE_8KB
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_8KB;
#else
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_16KB;
#endif
#else
#if CONFIG_ESP32S2_DATA_CACHE_8KB
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_8KB;
#else
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
cache_size = CACHE_SIZE_16KB;
#endif
#endif
cache_ways = CACHE_4WAYS_ASSOC;
#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B
cache_line_size = CACHE_LINE_SIZE_16B;
#else
cache_line_size = CACHE_LINE_SIZE_32B;
#endif
esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
esp_rom_Cache_Invalidate_DCache_All();
esp_rom_Cache_Enable_DCache(0);
#if !CONFIG_BOOTLOADER_ESP_IDF
/* The watchdog timer is enabled in the 1st stage (ROM) bootloader.
* We're done booting, so disable it.

10
soc/xtensa/esp32s2/soc.h
View file

@ -45,6 +45,16 @@ extern void esp_rom_Cache_Invalidate_ICache_All(void);
extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
extern int esp_rom_Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
/* data-cache related rom functions */
extern void esp_rom_Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways,
cache_line_size_t cache_line_size);
extern void esp_rom_Cache_Invalidate_DCache_All(void);
extern void esp_rom_Cache_Enable_DCache(uint32_t autoload);
extern void esp_rom_Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways,
cache_line_size_t cache_line_size);
/* ROM information related to SPI Flash chip timing and device */
extern esp_rom_spiflash_chip_t g_rom_flashchip;
extern uint8_t g_rom_spiflash_dummy_len_plus[];