From 65ec07fe3351eb9712b9dcb2af0ab203ba8d34c4 Mon Sep 17 00:00:00 2001 From: Wilfried Chauveau Date: Sun, 8 Oct 2023 00:27:41 +0100 Subject: [PATCH] =?UTF-8?q?arch:=20arm:=20cortex=5Fm:=20use=20cmsis=20API?= =?UTF-8?q?=C2=A0rather=20than=20assembly?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Asm is notoriously harder to maintain than C and requires core specific adaptation which impairs even more the readability of the code. Signed-off-by: Wilfried Chauveau --- arch/arm/core/irq_offload.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm/core/irq_offload.c b/arch/arm/core/irq_offload.c index 4e183c02e57..5dc1feccf7a 100644 --- a/arch/arm/core/irq_offload.c +++ b/arch/arm/core/irq_offload.c @@ -10,6 +10,7 @@ #include #include +#include volatile irq_offload_routine_t offload_routine; static const void *offload_param; @@ -22,14 +23,11 @@ void z_irq_do_offload(void) void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) { -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && defined(CONFIG_ASSERT) - /* ARMv6-M/ARMv8-M Baseline HardFault if you make a SVC call with - * interrupts locked. +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_BASELINE) \ + && defined(CONFIG_ASSERT) + /* ARMv6-M HardFault if you make a SVC call with interrupts locked. */ - unsigned int key; - - __asm__ volatile("mrs %0, PRIMASK;" : "=r" (key) : : "memory"); - __ASSERT(key == 0U, "irq_offload called with interrupts locked\n"); + __ASSERT(__get_PRIMASK() == 0U, "irq_offload called with interrupts locked\n"); #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE && CONFIG_ASSERT */ k_sched_lock();