drivers/fdcan: stm32: use new pinctrl API
Use the new pinctrl API to configure pins. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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274e83409d
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3 changed files with 12 additions and 21 deletions
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@ -5,11 +5,11 @@
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*/
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*/
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#include <drivers/can.h>
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#include <drivers/can.h>
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#include <drivers/pinctrl.h>
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#include <kernel.h>
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#include <kernel.h>
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#include <soc.h>
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#include <soc.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_rcc.h>
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#include "can_stm32fd.h"
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#include "can_stm32fd.h"
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#include <pinmux/pinmux_stm32.h>
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#include <logging/log.h>
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#include <logging/log.h>
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LOG_MODULE_DECLARE(can_driver, CONFIG_CAN_LOG_LEVEL);
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LOG_MODULE_DECLARE(can_driver, CONFIG_CAN_LOG_LEVEL);
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@ -72,9 +72,7 @@ static int can_stm32fd_init(const struct device *dev)
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int ret;
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int ret;
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/* Configure dt provided device signals when available */
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/* Configure dt provided device signals when available */
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ret = stm32_dt_pinctrl_configure(cfg->pinctrl,
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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ARRAY_SIZE(cfg->pinctrl),
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(uint32_t)mcan_cfg->can);
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if (ret < 0) {
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if (ret < 0) {
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LOG_ERR("CAN pinctrl setup failed (%d)", ret);
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LOG_ERR("CAN pinctrl setup failed (%d)", ret);
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return ret;
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return ret;
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@ -235,6 +233,9 @@ static void config_can_##inst##_irq(void) \
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#ifdef CONFIG_CAN_FD_MODE
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#ifdef CONFIG_CAN_FD_MODE
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#define CAN_STM32FD_CFG_INST(inst) \
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#define CAN_STM32FD_CFG_INST(inst) \
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\
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PINCTRL_DT_INST_DEFINE(inst) \
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\
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static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
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static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
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.msg_sram = (struct can_mcan_msg_sram *) \
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.msg_sram = (struct can_mcan_msg_sram *) \
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DT_INST_REG_ADDR_BY_NAME(inst, message_ram), \
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DT_INST_REG_ADDR_BY_NAME(inst, message_ram), \
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@ -258,12 +259,15 @@ static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
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.tx_delay_comp_offset = \
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.tx_delay_comp_offset = \
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DT_INST_PROP(inst, tx_delay_comp_offset) \
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DT_INST_PROP(inst, tx_delay_comp_offset) \
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}, \
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}, \
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.pinctrl = ST_STM32_DT_INST_PINCTRL(inst, 0), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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};
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};
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#else /* CONFIG_CAN_FD_MODE */
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#else /* CONFIG_CAN_FD_MODE */
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#define CAN_STM32FD_CFG_INST(inst) \
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#define CAN_STM32FD_CFG_INST(inst) \
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\
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PINCTRL_DT_INST_DEFINE(inst) \
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\
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static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
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static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
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.msg_sram = (struct can_mcan_msg_sram *) \
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.msg_sram = (struct can_mcan_msg_sram *) \
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DT_INST_REG_ADDR_BY_NAME(inst, message_ram), \
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DT_INST_REG_ADDR_BY_NAME(inst, message_ram), \
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@ -278,7 +282,7 @@ static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
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DT_INST_PROP_OR(inst, phase_seg1, 0), \
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DT_INST_PROP_OR(inst, phase_seg1, 0), \
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.ts2 = DT_INST_PROP_OR(inst, phase_seg2, 0), \
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.ts2 = DT_INST_PROP_OR(inst, phase_seg2, 0), \
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}, \
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}, \
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.pinctrl = ST_STM32_DT_INST_PINCTRL(inst, 0), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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};
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};
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#endif /* CONFIG_CAN_FD_MODE */
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#endif /* CONFIG_CAN_FD_MODE */
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@ -9,7 +9,6 @@
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#define ZEPHYR_DRIVERS_CAN_STM32FD_H_
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#define ZEPHYR_DRIVERS_CAN_STM32FD_H_
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#include "can_mcan.h"
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#include "can_mcan.h"
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#include <pinmux/pinmux_stm32.h>
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#define DEV_DATA(dev) ((struct can_stm32fd_data *)(dev)->data)
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#define DEV_DATA(dev) ((struct can_stm32fd_data *)(dev)->data)
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#define DEV_CFG(dev) ((const struct can_stm32fd_config *)(dev)->config)
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#define DEV_CFG(dev) ((const struct can_stm32fd_config *)(dev)->config)
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@ -18,8 +17,7 @@ struct can_stm32fd_config {
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struct can_mcan_msg_sram *msg_sram;
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struct can_mcan_msg_sram *msg_sram;
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void (*config_irq)(void);
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void (*config_irq)(void);
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struct can_mcan_config mcan_cfg;
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struct can_mcan_config mcan_cfg;
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/* CAN always has an RX and TX pin. Hence, hardcode it to two*/
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const struct pinctrl_dev_config *pcfg;
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const struct soc_gpio_pinctrl pinctrl[2];
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};
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};
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struct can_stm32fd_data {
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struct can_stm32fd_data {
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@ -2,15 +2,4 @@ description: Bosch m_can CAN-FD controller
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compatible: "st,stm32-fdcan"
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compatible: "st,stm32-fdcan"
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include: bosch,m-can.yaml
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include: ["bosch,m-can.yaml", "pinctrl-device.yaml"]
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properties:
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pinctrl-0:
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type: phandles
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required: false
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description: |
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GPIO pin configuration for CAN signals (RX, TX). We expect
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that the phandles will reference pinctrl nodes.
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For example the can1 would be
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pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
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