drivers: soc_flash_lpc: LPC legacy flash driver
Older LPC platforms use Flash IAP with a command style firmware command. Tested on LPC54114 platform. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit is contained in:
Andrei Gansari
Anas Nashif
parent
1e05bc2300
commit
6587c93aa9
5 changed files with 220 additions and 3 deletions
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@ -9,6 +9,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_FLASH_AT45 spi_flash_at45.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF soc_flash_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_RADIO_SYNC_TICKER soc_flash_nrf_ticker.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_MCUX soc_flash_mcux.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_LPC soc_flash_lpc.c)
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zephyr_library_sources_ifdef(CONFIG_FLASH_PAGE_LAYOUT flash_page_layout.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE flash_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM0 flash_sam0.c)
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@ -62,6 +62,8 @@ source "drivers/flash/Kconfig.at45"
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source "drivers/flash/Kconfig.nrf"
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source "drivers/flash/Kconfig.lpc"
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source "drivers/flash/Kconfig.mcux"
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source "drivers/flash/Kconfig.nios2_qspi"
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14
drivers/flash/Kconfig.lpc
Normal file
14
drivers/flash/Kconfig.lpc
Normal file
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@ -0,0 +1,14 @@
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# Copyright (c) 2020 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FLASH_LPC
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bool "LPC flash shim driver"
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depends on HAS_MCUX_IAP_LEGACY
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select FLASH_HAS_PAGE_LAYOUT
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select FLASH_HAS_DRIVER_ENABLED
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help
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Enables the LPC IAP flash shim driver.
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WARNING: This driver will disable the system interrupts for
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the duration of the flash erase/write operations. This will
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have an impact on the overall system performance - whether
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this is acceptable or not will depend on the use case.
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190
drivers/flash/soc_flash_lpc.c
Normal file
190
drivers/flash/soc_flash_lpc.c
Normal file
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@ -0,0 +1,190 @@
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/*
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* Copyright (c) 2020 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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#include <drivers/flash.h>
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#include <errno.h>
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#include <init.h>
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#include <soc.h>
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#include "flash_priv.h"
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#include "fsl_common.h"
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#include "fsl_flashiap.h"
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#if DT_NODE_HAS_STATUS(DT_INST(0, nxp_lpc_iap), okay)
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#define DT_DRV_COMPAT nxp_lpc_iap
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#else
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#error No matching compatible for soc_flash_lpc.c
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#endif
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#define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash)
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struct flash_priv {
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/* HACK: flash write protection is managed in software. */
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struct k_sem write_lock;
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uint32_t pflash_block_base;
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uint32_t sector_size;
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};
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static const struct flash_parameters flash_lpc_parameters = {
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#if DT_NODE_HAS_PROP(SOC_NV_FLASH_NODE, write_block_size)
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.write_block_size = DT_PROP(SOC_NV_FLASH_NODE, write_block_size),
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#else
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.write_block_size = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE,
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#endif
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.erase_value = 0xff,
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};
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static inline void prepare_erase_write(off_t offset, size_t len,
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uint32_t sector_size)
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{
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uint32_t start;
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uint32_t stop;
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start = offset / sector_size;
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stop = (offset+len-1) / sector_size;
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FLASHIAP_PrepareSectorForWrite(start, stop);
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}
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static int flash_lpc_erase(const struct device *dev, off_t offset, size_t len)
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{
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struct flash_priv *priv = dev->data;
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status_t rc;
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unsigned int key;
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uint32_t start;
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uint32_t stop;
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uint32_t page_size;
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if (k_sem_take(&priv->write_lock, K_NO_WAIT)) {
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return -EACCES;
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}
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key = irq_lock();
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prepare_erase_write(offset, len, priv->sector_size);
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page_size = flash_lpc_parameters.write_block_size;
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start = offset / page_size;
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stop = (offset+len-1) / page_size;
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rc = FLASHIAP_ErasePage(start, stop,
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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irq_unlock(key);
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k_sem_give(&priv->write_lock);
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return (rc == kStatus_FLASHIAP_Success) ? 0 : -EINVAL;
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}
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static int flash_lpc_read(const struct device *dev, off_t offset,
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void *data, size_t len)
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{
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struct flash_priv *priv = dev->data;
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uint32_t addr;
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addr = offset + priv->pflash_block_base;
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memcpy(data, (void *) addr, len);
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return 0;
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}
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static int flash_lpc_write(const struct device *dev, off_t offset,
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const void *data, size_t len)
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{
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struct flash_priv *priv = dev->data;
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uint32_t addr;
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status_t rc;
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unsigned int key;
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if (k_sem_take(&priv->write_lock, K_NO_WAIT)) {
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return -EACCES;
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}
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addr = offset + priv->pflash_block_base;
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key = irq_lock();
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prepare_erase_write(offset, len, priv->sector_size);
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rc = FLASHIAP_CopyRamToFlash(addr, (uint32_t *) data, len,
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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irq_unlock(key);
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k_sem_give(&priv->write_lock);
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return (rc == kStatus_FLASHIAP_Success) ? 0 : -EINVAL;
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}
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static int flash_lpc_write_protection(const struct device *dev, bool enable)
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{
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struct flash_priv *priv = dev->data;
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int rc = 0;
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if (enable) {
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rc = k_sem_take(&priv->write_lock, K_FOREVER);
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} else {
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k_sem_give(&priv->write_lock);
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}
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return rc;
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}
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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static const struct flash_pages_layout dev_layout = {
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.pages_count = DT_REG_SIZE(SOC_NV_FLASH_NODE) /
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DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
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.pages_size = DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
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};
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static void flash_lpc_pages_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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*layout = &dev_layout;
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*layout_size = 1;
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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static const struct flash_parameters *
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flash_lpc_get_parameters(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return &flash_lpc_parameters;
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}
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static struct flash_priv flash_data;
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static const struct flash_driver_api flash_lpc_api = {
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.write_protection = flash_lpc_write_protection,
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.erase = flash_lpc_erase,
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.write = flash_lpc_write,
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.read = flash_lpc_read,
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.get_parameters = flash_lpc_get_parameters,
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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.page_layout = flash_lpc_pages_layout,
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#endif
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};
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static int flash_lpc_init(const struct device *dev)
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{
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struct flash_priv *priv = dev->data;
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k_sem_init(&priv->write_lock, 0, 1);
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priv->pflash_block_base = DT_REG_ADDR(SOC_NV_FLASH_NODE);
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#if defined(FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES)
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priv->sector_size = FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;
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#else
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#error "Sector size not set"
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#endif
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, flash_lpc_init, device_pm_control_nop,
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&flash_data, NULL, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_lpc_api);
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@ -53,9 +53,19 @@
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reg = <0x4000000 DT_SIZE_K(32)>;
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};
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flash0:flash@0 {
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iap: flash-controller@4009c000 {
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compatible = "nxp,lpc-iap";
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label = "FLASH_IAP";
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reg = <0x4009c000 0x18>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 DT_SIZE_K(256)>;
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label = "LPC_FLASH";
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erase-block-size = <256>;
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write-block-size = <256>;
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};
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};
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gpio0: gpio@0 {
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