diff --git a/boards/arm/mimxrt1060_evk/CMakeLists.txt b/boards/arm/mimxrt1060_evk/CMakeLists.txt
new file mode 100644
index 00000000000..c797d3ce385
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/CMakeLists.txt
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_library_sources(pinmux.c)
diff --git a/boards/arm/mimxrt1060_evk/Kconfig b/boards/arm/mimxrt1060_evk/Kconfig
new file mode 100644
index 00000000000..fd459cb4062
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/Kconfig
@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_MIMXRT1060_EVK
+
+choice
+	prompt "Code location selection"
+	default CODE_ITCM
+
+config CODE_ITCM
+	bool "Link code into internal instruction tightly coupled memory (ITCM)"
+
+config CODE_HYPERFLASH
+	bool "Link code into external HyperFlash memory"
+
+config CODE_QSPI
+	bool "Link code into external QSPI memory"
+
+endchoice
+
+endif # BOARD_MIMXRT1050_EVK
diff --git a/boards/arm/mimxrt1060_evk/Kconfig.board b/boards/arm/mimxrt1060_evk/Kconfig.board
new file mode 100644
index 00000000000..9eeee7e0580
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/Kconfig.board
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_MIMXRT1060_EVK
+	bool "NXP MIMXRT1060-EVK"
+	depends on SOC_SERIES_IMX_RT
+	select SOC_PART_NUMBER_MIMXRT1062DVL6A
diff --git a/boards/arm/mimxrt1060_evk/Kconfig.defconfig b/boards/arm/mimxrt1060_evk/Kconfig.defconfig
new file mode 100644
index 00000000000..42d718d2969
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/Kconfig.defconfig
@@ -0,0 +1,38 @@
+# Kconfig - MIMXRT1060-EVK board
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_MIMXRT1060_EVK
+
+config BOARD
+	default "mimxrt1060_evk"
+
+if GPIO_MCUX_IGPIO
+
+config GPIO_MCUX_IGPIO_1
+	def_bool y
+
+config GPIO_MCUX_IGPIO_5
+	def_bool y
+
+endif # GPIO_MCUX_IGPIO
+
+if UART_MCUX_LPUART
+
+config UART_MCUX_LPUART_1
+	def_bool y
+
+endif # UART_MCUX_LPUART
+
+if CODE_HYPERFLASH || CODE_QSPI
+
+# Reserve space for the IVT
+config TEXT_SECTION_OFFSET
+	default 0x2000
+
+endif
+
+endif # BOARD_MIMXRT1060_EVK
diff --git a/boards/arm/mimxrt1060_evk/board.cmake b/boards/arm/mimxrt1060_evk/board.cmake
new file mode 100644
index 00000000000..290cb2925e0
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/board.cmake
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCIMXRT1062")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/arm/mimxrt1060_evk/board.h b/boards/arm/mimxrt1060_evk/board.h
new file mode 100644
index 00000000000..4ac0cf69b2f
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/board.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2018, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+#endif /* __INC_BOARD_H */
diff --git a/boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.jpg b/boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.jpg
new file mode 100644
index 00000000000..f676d50d9f8
Binary files /dev/null and b/boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.jpg differ
diff --git a/boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.rst b/boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.rst
new file mode 100644
index 00000000000..848e73a2262
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.rst
@@ -0,0 +1,196 @@
+.. _mimxrt1060_evk:
+
+NXP MIMXRT1060-EVK
+##################
+
+Overview
+********
+
+The i.MX RT1060 is the latest addition to the industry's first crossover
+processor series and expands the i.MX RT series to three scalable families.
+The i.MX RT1060 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin
+compatibility with i.MX RT1050. This new series introduces additional features
+ideal for real-time applications such as High-Speed GPIO, CAN-FD, and
+synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1060 runs on the
+Arm® Cortex-M7® core at 600 MHz.
+
+.. image:: mimxrt1060_evk.jpg
+   :width: 720px
+   :align: center
+   :alt: MIMXRT1060-EVK
+
+Hardware
+********
+
+- MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory)
+
+- Memory
+
+  - 256 Mbit SDRAM
+  - 64 Mbit QSPI Flash
+  - 512 Mbit Hyper Flash
+  - TF socket for SD card
+
+- Display
+
+  - LCD connector
+
+- Ethernet
+
+  - 10/100 Mbit/s Ethernet PHY
+
+- USB
+
+  - USB 2.0 OTG connector
+  - USB 2.0 host connector
+
+- Audio
+
+  - 3.5 mm audio stereo headphone jack
+  - Board-mounted microphone
+  - Left and right speaker out connectors
+
+- Power
+
+  - 5 V DC jack
+
+- Debug
+
+  - JTAG 20-pin connector
+  - OpenSDA with DAPLink
+
+- Sensor
+
+  - FXOS8700CQ 6-axis e-compass
+  - CMOS camera sensor interface
+
+- Expansion port
+
+  - Arduino interface
+
+- CAN bus connector
+
+For more information about the MIMXRT1060 SoC and MIMXRT1060-EVK board, see
+these references:
+
+- `i.MX RT1060 Website`_
+- `i.MX RT1060 Datasheet`_
+- `i.MX RT1060 Reference Manual`_
+- `MIMXRT1060-EVK Website`_
+- `MIMXRT1060-EVK User Guide`_
+- `MIMXRT1060-EVK Schematics`_
+
+Supported Features
+==================
+
+The mimxrt1060_evk board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+``boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig``
+
+Other hardware features are not currently supported by the port.
+
+Connections and I/Os
+====================
+
+The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers.
+
++---------------+-----------------+---------------------------+
+| Name          | Function        | Usage                     |
++===============+=================+===========================+
+| GPIO_AD_B0_09 | GPIO            | LED                       |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_12 | LPUART1_TX      | UART Console              |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_13 | LPUART1_RX      | UART Console              |
++---------------+-----------------+---------------------------+
+| WAKEUP        | GPIO            | SW0                       |
++---------------+-----------------+---------------------------+
+
+System Clock
+============
+
+The MIMXRT1060 SoC is configured to use the 24 MHz external oscillator on the
+board with the on-chip PLL to generate a 600 MHz core clock.
+
+Serial Port
+===========
+
+The MIMXRT1060 SoC has eight UARTs. One is configured for the console and the
+remaining are not used.
+
+Programming and Debugging
+*************************
+
+The MIMXRT1060-EVK includes the :ref:`nxp_opensda` serial and debug adapter
+built into the board to provide debugging, flash programming, and serial
+communication over USB.
+
+To use the Segger J-Link tools with OpenSDA, follow the instructions in the
+:ref:`nxp_opensda_jlink` page using the `Segger J-Link OpenSDA V2.1 Firmware`_.
+The Segger J-Link tools are the default for this board, therefore it is not
+necessary to set ``OPENSDA_FW=jlink`` explicitly when you invoke ``make
+debug``.
+
+With these mechanisms, applications for the ``mimxrt1060_evk`` board
+configuration can be built and debugged in the usual way (see
+:ref:`build_an_application` and :ref:`application_run` for more details).
+
+The pyOCD tools do not yet support this SoC.
+
+Flashing
+========
+
+The Segger J-Link firmware does not support command line flashing, therefore
+the usual ``flash`` build system target is not supported.
+Instead, see the https://www.nxp.com/docs/en/application-note/AN12108.pdf for flashing instructions.
+
+
+Debugging
+=========
+
+This example uses the :ref:`hello_world` sample with the
+:ref:`nxp_opensda_jlink` tools. Run the following to build your Zephyr
+application, invoke the J-Link GDB server, attach a GDB client, and program
+your Zephyr application to flash. It will leave you at a GDB prompt.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mimxrt1060_evk
+   :goals: debug
+
+
+.. _MIMXRT1060-EVK Website:
+   https://www.nxp.com/support/developer-resources/software-development-tools/mcuxpresso-software-and-tools/mimxrt1060-evk-i.mx-rt1060-evaluation-kit:MIMXRT1060-EVK
+
+.. _MIMXRT1060-EVK User Guide:
+   https://www.nxp.com/docs/en/user-guide/UM11151.PDF
+
+.. _MIMXRT1060-EVK Schematics:
+   https://www.nxp.com/webapp/Download?colCode=MIMXRT1060-EVK-DESIGN-FILE-A2
+
+.. _i.MX RT1060 Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060
+
+.. _i.MX RT1060 Datasheet:
+   https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf
+
+.. _i.MX RT1060 Reference Manual:
+   https://www.nxp.com/docs/en/reference-manual/IMXRT1060RM.pdf
+
+.. _Segger J-Link OpenSDA V2.1 Firmware:
+   https://www.segger.com/downloads/jlink/OpenSDA_V2_1.bin
diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts
new file mode 100644
index 00000000000..266b0ccee34
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2018, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_rt.dtsi>
+
+/ {
+	model = "NXP MIMXRT1060-EVK board";
+	compatible = "nxp,mimxrt1062";
+
+	aliases {
+		gpio-1= &gpio1;
+		gpio-2= &gpio2;
+		gpio-3= &gpio3;
+		gpio-4= &gpio4;
+		gpio-5= &gpio5;
+		uart-1 = &uart1;
+		led0 = &green_led;
+		sw0 = &user_button;
+	};
+
+	chosen {
+#if defined(CONFIG_CODE_ITCM)
+		zephyr,flash = &itcm0;
+#elif defined(CONFIG_CODE_HYPERFLASH)
+		zephyr,flash = &hyperflash0;
+#elif defined(CONFIG_CODE_QSPI)
+		zephyr,flash = &qspi0;
+#endif
+		zephyr,sram = &dtcm0;
+		zephyr,console = &uart1;
+	};
+
+	sdram0: memory@80000000 {
+		/* Micron MT48LC16M16A2B4-6AIT:G */
+		device_type = "memory";
+		reg = <0x80000000 0x2000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led: led-1 {
+			gpios = <&gpio1 9 GPIO_INT_ACTIVE_LOW>;
+			label = "User LD1";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button-1 {
+			label = "User SW8";
+			gpios = <&gpio5 0 GPIO_INT_ACTIVE_LOW>;
+		};
+	};
+};
+
+&flexspi0 {
+	hyperflash0: hyperflash@60000000 {
+		/* Cypress S26KS512SDPBHI02 */
+		reg = <0x60000000 0x4000000>;
+#if defined(CONFIG_CODE_HYPERFLASH)
+		status = "ok";
+#else
+		status = "disabled";
+#endif
+	};
+
+	qspi0: qspi@60000000 {
+		/* ISSI IS25WP064AJBLE */
+		reg = <0x60000000 0x800000>;
+#if defined(CONFIG_CODE_QSPI)
+		status = "ok";
+#else
+		status = "disabled";
+#endif
+	};
+};
+
+&uart1 {
+	status = "ok";
+	current-speed = <115200>;
+};
diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml
new file mode 100644
index 00000000000..72d42905f08
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt1060_evk
+name: NXP MIMXRT1060-EVK
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 128
+flash: 128
diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig
new file mode 100644
index 00000000000..dc60eaa9e6e
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig
@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_ARM=y
+CONFIG_SOC_MIMXRT1062=y
+CONFIG_SOC_SERIES_IMX_RT=y
+CONFIG_BOARD_MIMXRT1060_EVK=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_GPIO=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000
diff --git a/boards/arm/mimxrt1060_evk/pinmux.c b/boards/arm/mimxrt1060_evk/pinmux.c
new file mode 100644
index 00000000000..21637fda9e1
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/pinmux.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <fsl_iomuxc.h>
+
+static int mimxrt1060_evk_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	CLOCK_EnableClock(kCLOCK_Iomuxc);
+	CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+	/* LED */
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
+
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
+			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
+			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
+
+	/* SW0 */
+	IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
+
+#ifdef CONFIG_UART_MCUX_LPUART_1
+	/* LPUART1 TX/RX */
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
+
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
+			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
+			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
+
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
+			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
+			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
+#endif
+
+	return 0;
+}
+
+SYS_INIT(mimxrt1060_evk_init, PRE_KERNEL_1, 0);