michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: pinctrl: bouffalolab: Add bflb pinctrl driver

Browse source 
Add Bouffalo Lab pinctrl driver.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2024-01-27 10:54:29 +01:00 • committed by Benjamin Cabé
commit 6520633a90
11 changed files with 334 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
drivers/pinctrl/CMakeLists.txt
View file

@ -9,6 +9,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_AMBIQ pinctrl_ambiq.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS2 pinctrl_arm_mps2.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS3 pinctrl_arm_mps3.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_V2M_BEETLE pinctrl_arm_v2m_beetle.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_BFLB pinctrl_bflb.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c)

1
drivers/pinctrl/Kconfig
View file

@ -35,6 +35,7 @@ config PINCTRL_DYNAMIC
peripheral at early boot stages depending on a certain input.
source "drivers/pinctrl/Kconfig.b91"
source "drivers/pinctrl/Kconfig.bflb"
source "drivers/pinctrl/Kconfig.ambiq"
source "drivers/pinctrl/Kconfig.arm_mps2"
source "drivers/pinctrl/Kconfig.arm_mps3"

10
drivers/pinctrl/Kconfig.bflb Normal file
View file

@ -0,0 +1,10 @@
# Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
config PINCTRL_BFLB
bool "Bouffalo Lab pin control driver"
depends on DT_HAS_BFLB_PINCTRL_ENABLED
default y
help
Bouffalo Lab pin control driver

45
drivers/pinctrl/pinctrl_bflb.c Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <bflb_pinctrl.h>
#include <bflb_glb.h>
#include <bflb_gpio.h>
/* clang-format off */
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
GLB_GPIO_Cfg_Type pincfg;
uint8_t i;
ARG_UNUSED(reg);
for (i = 0U; i < pin_cnt; i++) {
pincfg.gpioFun = BFLB_PINMUX_GET_FUN(pins[i]);
pincfg.gpioMode = BFLB_PINMUX_GET_MODE(pins[i]);
pincfg.gpioPin = BFLB_PINMUX_GET_PIN(pins[i]);
pincfg.pullType = BFLB_PINMUX_GET_PULL_MODES(pins[i]);
pincfg.smtCtrl = BFLB_PINMUX_GET_SMT(pins[i]);
pincfg.drive = BFLB_PINMUX_GET_DRIVER_STRENGTH(pins[i]);
if (pincfg.gpioFun == BFLB_PINMUX_FUN_INST_uart0) {
GLB_UART_Fun_Sel(pincfg.gpioPin % 8,
(BFLB_PINMUX_GET_INST(pins[i]))
* 0x4U /* rts, cts, rx, tx */
+ BFLB_PINMUX_GET_SIGNAL(pins[i])
);
}
GLB_GPIO_Init(&pincfg);
}
return 0;
}
/* clang-format on */

35
dts/bindings/gpio/bflb,gpio.yaml Normal file
View file

@ -0,0 +1,35 @@
# Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
description: Bouffalo Lab GPIO node
compatible: "bflb,gpio"
include:
- name: base.yaml
- name: gpio-controller.yaml
properties:
reg:
required: true
interrupts:
required: true
"#gpio-cells":
const: 2
"#bflb,pin-cells":
type: int
required: true
const: 2
description: Number of items to expect in a bflb,pins specifier
gpio-cells:
- pin
- flags
bflb,pin-cells:
- pin
- peripheral

91
dts/bindings/pinctrl/bflb,pinctrl.yaml Normal file
View file

@ -0,0 +1,91 @@
# Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
description: Bouffalo Lab Pinctrl node
compatible: "bflb,pinctrl"
include: base.yaml
properties:
"#address-cells":
required: true
const: 1
"#size-cells":
required: true
const: 1
child-binding:
description: |
Bouffalo Lab pin controller pin configuration nodes. Each node is composed
by one or more groups, each defining the configuration for a set of pins.
child-binding:
description: |
Bouffalo Lab pin controller pin configuration group. Each group contains
a list of pins sharing the same set of properties. Example:
uart0_default: uart0_default {
/* group 1 (name is arbitrary) */
group1 {
/* configure to uart0 function plus modem interrupt, pin 7 as UART_RX
pin 16 as UART_TX and finally pin 18 as gpio */
pinmux = <GPIO7_UART0_RX>,
<GPIO16_UART0_TX>;
bias-pull-up;
input-schmitt-enable;
};
};
uart0_sleep: uart0_sleep {
group1 {
pinmux = <GPIO7_UART0_RX>,
<GPIO16_UART0_TX>;
bias-high-impedance;
};
};
The list of supported standard properties:
- bias-high-impedance: Disable pull-up/down (default behavior, not
required).
- bias-pull-up: Enable pull-up resistor.
- bias-pull-down: Enable pull-down resistor.
- input-enable: Enable GPIO as input (default behavior, not required).
- input-schmitt-enable: Enable Schimitt Trigger when GPIO is Input.
- output-enable: Enable GPIO as output.
Note that bias options are mutually exclusive. It is the same with GPIO
input/output enable options.
include:
- name: pincfg-node.yaml
property-allowlist:
- bias-high-impedance
- bias-pull-down
- bias-pull-up
- input-enable
- input-schmitt-enable
- output-enable
properties:
pinmux:
required: true
type: array
description: |
An array of pins sharing the same group properties. The pins should be
defined using the BFLB_PINMUX utility macro that encode all the pin
route matrix.
drive-strength:
type: int
default: 0
enum:
- 0 # Default value, lower strength, 8mA
- 1 # 9.6mA
- 2 # 11.2mA
- 3 # highest strength, 12.8mA
description: |
Pin drive strength. It tunes pin max current where 0 means lower
value, which is the default, and 3 represents max drive strength.
The driver will automatically apply the default value (8mA) to all
pins to save power.

23
dts/riscv/bouffalolab/bl60x.dtsi
View file

@ -6,6 +6,8 @@
#include <freq.h>
#include <mem.h>
#include <dt-bindings/pinctrl/bl60x-pinctrl.h>
#include <dt-bindings/pinctrl/bflb-common-pinctrl.h>
/ {
#address-cells = <1>;
@ -60,6 +62,27 @@
interrupts-extended = <&ictrl 7>;
};
pinctrl: pin-controller@40000000 {
compatible = "bflb,pinctrl";
reg = <0x40000000 0x1000>;
ranges = <0x40000000 0x40000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
glb: gpio@40000000 {
compatible = "bflb,gpio";
reg = <0x40000000 0x1000>;
#gpio-cells = <2>;
#bflb,pin-cells = <2>;
status = "disabled";
gpio-controller;
interrupts = <1 0>;
interrupt-parent = <&ictrl>;
};
};
spi0: spi@4000a200 {
compatible = "bflb,spi";
reg = <0x4000a200 0x100>;

82
include/zephyr/drivers/pinctrl/pinctrl_soc_bflb_common.h Normal file
View file

@ -0,0 +1,82 @@
/*
* Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* Bouffalo Lab SoC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_BFLB_COMMON_H_
#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_BFLB_COMMON_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
/* clang-format off */
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
/**
* @brief BFLB pincfg bit field.
* @anchor BFLB_PINMUX
*
* Fields:
*
* - 24..31: pin
* - 20..23: signal
* - 18..19: mode
* - 16..17: instance
* - 8..15: function
* - 7: reserved
* - 6: GPIO Output Enable
* - 5: Pull Down
* - 4: Pull Up
* - 2..3: Driver Strength
* - 1: Schmitt trigger (SMT)
* - 0: reserved
*/
typedef uint32_t pinctrl_soc_pin_t;
/**
* @brief Utility macro to initialize each pin.
*
* @param node_id Node identifier.
* @param prop Property name.
* @param idx Property entry index.
*/
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
((DT_PROP_BY_IDX(node_id, prop, idx)) \
| (DT_PROP(node_id, bias_pull_up) << BFLB_PINMUX_PULL_UP_POS) \
| (DT_PROP(node_id, bias_pull_down) << BFLB_PINMUX_PULL_DOWN_POS) \
| (DT_PROP(node_id, output_enable) << BFLB_PINMUX_OE_POS) \
| (DT_PROP(node_id, input_schmitt_enable) << BFLB_PINMUX_SMT_POS) \
| (DT_ENUM_IDX(node_id, drive_strength) << BFLB_PINMUX_DRIVER_STRENGTH_POS) \
),
/**
* @brief Utility macro to initialize state pins contained in a given property.
*
* @param node_id Node identifier.
* @param prop Property name describing state pins.
*/
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, \
Z_PINCTRL_STATE_PIN_INIT)}
/** @endcond */
#ifdef __cplusplus
}
#endif
/* clang-format on */
#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_BFLB_COMMON_H_ */

14
modules/hal_bouffalolab/include/bflb_gpio.h Normal file
View file

@ -0,0 +1,14 @@
/*
* Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_HAL_BFLB_GPIO_H_
#define ZEPHYR_HAL_BFLB_GPIO_H_
#ifdef CONFIG_SOC_SERIES_BL60X
#include <bl602_gpio.h>
#endif
#endif /* ZEPHYR_HAL_BFLB_GPIO_H_ */

15
modules/hal_bouffalolab/include/bflb_pinctrl.h Normal file
View file

@ -0,0 +1,15 @@
/*
* Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_HAL_BFLB_PINCTRL_H_
#define ZEPHYR_HAL_BFLB_PINCTRL_H_
#ifdef CONFIG_SOC_SERIES_BL60X
#include <zephyr/dt-bindings/pinctrl/bl60x-pinctrl.h>
#endif
#include <zephyr/dt-bindings/pinctrl/bflb-common-pinctrl.h>
#endif /* ZEPHYR_HAL_BFLB_PINCTRL_H_ */

17
soc/bouffalolab/common/pinctrl_soc.h Normal file
View file

@ -0,0 +1,17 @@
/*
* Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* Bouffalo Lab SoC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_SOC_RISCV_BFLB_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RISCV_BFLB_COMMON_PINCTRL_SOC_H_
#include <zephyr/drivers/pinctrl/pinctrl_soc_bflb_common.h>
#endif /* ZEPHYR_SOC_RISCV_BFLB_COMMON_PINCTRL_SOC_H_ */