gpio: Add QMSI-based implementation
Introduce the GPIO QMSI-based implementation. This is basically a shim layer that implement's Zephyr's GPIO APIs on top of QMSI drivers. This is an alternative driver that conflicts with the previous GPIO_DW implementation. In order to enable it you must set: - CONFIG_GPIO=n - CONFIG_GPIO_QMSI=y - CONFIG_GPIO_0=y - CONFIG_QMSI_DRIVERS=y - CONFIG_QMSI_INTALL_PATH="PATH_TO_QMSI" Note that this driver currently only supports one controller instance, GPIO_0. It is implemented this way due to a limitation from the current version of QMSI. QMSI versions later than 1.0 doesn't have this limitation. Missing: - support multiple controller instances (gpio_0, gpio_1, etc); - enable level triggered interrupts in sync with system clock, through setting INT_CLOCK_SYNC properly. Change-Id: Ib61b153dae9741806a9a31d7dc1f82b96d000fbe Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This commit is contained in:
Jesus Sanchez-Palencia
Anas Nashif
parent
41771e5b1c
commit
6504b7e72a
5 changed files with 347 additions and 2 deletions
284
drivers/gpio/gpio_qmsi.c
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284
drivers/gpio/gpio_qmsi.c
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/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <device.h>
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#include <drivers/ioapic.h>
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#include <gpio.h>
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#include <init.h>
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#include <nanokernel.h>
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#include <sys_io.h>
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#include "qm_gpio.h"
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#include "qm_scss.h"
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#define INTEN 0x30
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#define INTMASK 0x34
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#define PORTA_EOI 0x4c
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#define INT_GPIO_MASK 0x6c
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struct gpio_qmsi_config {
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qm_gpio_t gpio;
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void *addr;
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uint8_t num_pins;
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};
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struct gpio_qmsi_runtime {
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gpio_callback_t callback;
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uint32_t pin_callbacks;
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uint8_t port_callback;
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};
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/*
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* TODO: Zephyr's API is not clear about the behavior of the this
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* application callback. This topic is currently under
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* discussion, so this implementation will be fixed as soon as a
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* decision is made.
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*/
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static void gpio_qmsi_0_int_callback(uint32_t status)
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{
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struct device *port = device_get_binding(CONFIG_GPIO_QMSI_0_NAME);
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struct gpio_qmsi_config *config = port->config->config_info;
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struct gpio_qmsi_runtime *context = port->driver_data;
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const uint32_t enabled_mask = context->pin_callbacks & status;
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int bit;
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if (!context->callback)
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return;
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if (context->port_callback) {
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context->callback(port, status);
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return;
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}
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if (!enabled_mask)
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return;
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for (bit = 0; bit < config->num_pins; bit++) {
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if (enabled_mask & (1 << bit)) {
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context->callback(port, bit);
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}
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}
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}
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static void qmsi_write_bit(uint32_t *target, uint8_t bit, uint8_t value)
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{
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if (value) {
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sys_set_bit((uintptr_t) target, bit);
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} else {
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sys_clear_bit((uintptr_t) target, bit);
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}
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}
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static inline void qmsi_pin_config(struct device *port, uint32_t pin, int flags)
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{
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struct gpio_qmsi_config *gpio_config = port->config->config_info;
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qm_gpio_reg_t *gpio_reg = gpio_config->addr;
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qm_gpio_t gpio = gpio_config->gpio;
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/* Save int mask and mask this pin while we configure the port.
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* We do this to avoid "spurious interrupts", which is a behavior
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* we have observed on QMSI and that still needs investigation.
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*/
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uint32_t intmask = gpio_reg->gpio_intmask;
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qm_gpio_port_config_t cfg = { 0 };
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sys_set_bit((uint32_t) gpio_reg + INTMASK, pin);
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qm_gpio_get_config(gpio, &cfg);
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qmsi_write_bit(&cfg.direction, pin, (flags & GPIO_DIR_MASK));
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if (flags & GPIO_INT) {
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qmsi_write_bit(&cfg.int_type, pin, (flags & GPIO_INT_EDGE));
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qmsi_write_bit(&cfg.int_polarity, pin, (flags & GPIO_INT_ACTIVE_HIGH));
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qmsi_write_bit(&cfg.int_debounce, pin, (flags & GPIO_INT_DEBOUNCE));
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qmsi_write_bit(&cfg.int_bothedge, pin, (flags & GPIO_INT_DOUBLE_EDGE));
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qmsi_write_bit(&cfg.int_en, pin, 1);
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}
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/* FIXME: for multiple GPIO ports */
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cfg.callback = gpio_qmsi_0_int_callback;
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qm_gpio_set_config(gpio, &cfg);
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/* Recover the original interrupt mask for this port. */
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sys_write32(intmask, (uint32_t) gpio_reg + INTMASK);
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}
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static inline void qmsi_port_config(struct device *port, int flags)
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{
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struct gpio_qmsi_config *gpio_config = port->config->config_info;
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uint8_t num_pins = gpio_config->num_pins;
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int i;
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for (i = 0; i < num_pins; i++) {
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qmsi_pin_config(port, i, flags);
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}
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}
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static inline int gpio_qmsi_config(struct device *port, int access_op,
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uint32_t pin, int flags)
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{
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if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
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((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
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return DEV_INVALID_CONF;
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}
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if (access_op == GPIO_ACCESS_BY_PIN) {
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qmsi_pin_config(port, pin, flags);
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} else {
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qmsi_port_config(port, flags);
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}
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return DEV_OK;
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}
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static inline int gpio_qmsi_write(struct device *port, int access_op,
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uint32_t pin, uint32_t value)
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{
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struct gpio_qmsi_config *gpio_config = port->config->config_info;
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qm_gpio_t gpio = gpio_config->gpio;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) {
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qm_gpio_set_pin(gpio, pin);
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} else {
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qm_gpio_clear_pin(gpio, pin);
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}
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} else {
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qm_gpio_write_port(gpio, value);
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}
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return DEV_OK;
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}
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static inline int gpio_qmsi_read(struct device *port, int access_op,
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uint32_t pin, uint32_t *value)
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{
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struct gpio_qmsi_config *gpio_config = port->config->config_info;
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qm_gpio_t gpio = gpio_config->gpio;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = qm_gpio_read_pin(gpio, pin);
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} else {
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*value = qm_gpio_read_port(gpio);
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}
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return DEV_OK;
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}
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static inline int gpio_qmsi_set_callback(struct device *port,
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gpio_callback_t callback)
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{
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struct gpio_qmsi_runtime *context = port->driver_data;
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context->callback = callback;
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return DEV_OK;
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}
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static inline int gpio_qmsi_enable_callback(struct device *port, int access_op,
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uint32_t pin)
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{
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struct gpio_qmsi_config *gpio_config = port->config->config_info;
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struct gpio_qmsi_runtime *context = port->driver_data;
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uint32_t reg = (uint32_t) gpio_config->addr;
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sys_set_bit(reg + PORTA_EOI, pin);
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sys_clear_bit(reg + INTMASK, pin);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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context->pin_callbacks |= BIT(pin);
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} else {
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context->port_callback = 1;
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}
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return DEV_OK;
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}
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static inline int gpio_qmsi_disable_callback(struct device *port, int access_op,
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uint32_t pin)
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{
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struct gpio_qmsi_config *gpio_config = port->config->config_info;
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struct gpio_qmsi_runtime *context = port->driver_data;
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uint32_t reg = (uint32_t) gpio_config->addr;
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sys_set_bit(reg + INTMASK, pin);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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context->pin_callbacks &= ~BIT(pin);
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} else {
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context->port_callback = 0;
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}
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return DEV_OK;
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}
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static inline int gpio_qmsi_suspend_port(struct device *port)
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{
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return DEV_NO_SUPPORT;
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}
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static inline int gpio_qmsi_resume_port(struct device *port)
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{
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return DEV_NO_SUPPORT;
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}
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static struct gpio_driver_api api_funcs = {
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.config = gpio_qmsi_config,
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.write = gpio_qmsi_write,
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.read = gpio_qmsi_read,
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.set_callback = gpio_qmsi_set_callback,
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.enable_callback = gpio_qmsi_enable_callback,
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.disable_callback = gpio_qmsi_disable_callback,
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.suspend = gpio_qmsi_suspend_port,
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.resume = gpio_qmsi_resume_port
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};
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int gpio_qmsi_init(struct device *port)
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{
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struct gpio_qmsi_config *gpio_config = port->config->config_info;
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uint32_t reg = (uint32_t) gpio_config->addr;
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clk_periph_enable(CLK_PERIPH_GPIO_REGISTER |
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CLK_PERIPH_GPIO_INTERRUPT | CLK_PERIPH_GPIO_DB);
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/* mask and disable interrupts */
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sys_write32(~(0), reg + INTMASK);
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sys_write32(0, reg + INTEN);
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sys_write32(~(0), reg + PORTA_EOI);
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irq_connect(CONFIG_GPIO_QMSI_0_IRQ, CONFIG_GPIO_QMSI_0_PRI, qm_gpio_isr_0,
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0, IOAPIC_EDGE | IOAPIC_HIGH);
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/* Enable GPIO IRQ and unmask interrupts for Lakemont. */
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sys_clear_bit(QM_SCSS_INT_BASE + INT_GPIO_MASK, 0);
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irq_enable(CONFIG_GPIO_QMSI_0_IRQ);
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port->driver_api = &api_funcs;
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return DEV_OK;
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}
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static struct gpio_qmsi_config gpio_0_config = {
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.gpio = QM_GPIO_0,
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.addr = &QM_GPIO[0],
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.num_pins = QM_NUM_GPIO_PINS,
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};
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static struct gpio_qmsi_runtime gpio_0_runtime;
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DECLARE_DEVICE_INIT_CONFIG(gpio_0, CONFIG_GPIO_QMSI_0_NAME,
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&gpio_qmsi_init, &gpio_0_config);
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SYS_DEFINE_DEVICE(gpio_0, &gpio_0_runtime, SECONDARY,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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