Revert "scripts: gen_defines: re-work write_clocks() with augmented nodes"
This reverts commit c048f872d7
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Reverted as the changes to gen_defines.py break things.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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1ebe6f2bdd
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1 changed files with 16 additions and 75 deletions
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@ -790,8 +790,6 @@ def write_phandle_val_list_entry(node, entry, i, ident):
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def write_clocks(node):
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# Writes clock information.
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#
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# Like write_regs(), but for clocks.
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#
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# Most of this ought to be handled in write_props(), but the identifiers
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# that get generated for 'clocks' are inconsistent with the with other
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# 'phandle-array' properties.
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@ -801,87 +799,30 @@ def write_clocks(node):
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if "clocks" not in node.props:
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return
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# Maps a clock_i to (primary_controller, primary_data,
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# primary_frequency) macros for that clock index
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clock_i2primary_cdf = {}
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def write_clocks_for_ident(node, ident):
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clocks = node.props["clocks"].val
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for clock_i, clock in enumerate(clocks):
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primary_cdf = clock_i2primary_cdf.get(clock_i)
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if primary_cdf is None:
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# Print the primary macros and save them for future use
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clock_i2primary_cdf[clock_i] = primary_cdf = \
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write_clock_primary(ident, clock_i, clock)
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else:
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# Print other macros in terms of primary macros
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write_clock_other(ident, clock_i, clock, primary_cdf)
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def write_clock_primary(ident, clock_i, clock):
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# Write clock macros for the primary identifier 'ident'.
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# Return a (primary_controller, primary_data,
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# primary_frequency) tuple to use for other idents.
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for clock_i, clock in enumerate(node.props["clocks"].val):
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controller = clock.controller
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# If the clock controller has a label property:
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# DT_<IDENT>_CLOCK_CONTROLLER <LABEL_PROPERTY>
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if controller.label:
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# FIXME this is replicating previous behavior that didn't
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# generate an indexed controller bug-for-bug. There's a
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# missing _{clock_i} at the end of the f-string.
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prim_controller = out_s(f"{ident}_CLOCK_CONTROLLER",
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controller.label)
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else:
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prim_controller = None
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# For each additional cell in the controller + data:
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# DT_<IDENT>_CLOCK_<CELL_NAME>_<clock_i> <CELL_VALUE>
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#
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# Cell names are from the controller binding's "clock-cells".
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prim_data = []
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if controller.label is not None:
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out_node_s(node, "CLOCK_CONTROLLER", controller.label)
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for name, val in clock.data.items():
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prim_macro = out(f"{ident}_CLOCK_{str2ident(name)}_{clock_i}", val)
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prim_data.append(prim_macro)
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if clock_i == 0:
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out(f"{ident}_CLOCK_{str2ident(name)}", prim_macro)
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clk_name_alias = "CLOCK_" + str2ident(name)
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else:
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clk_name_alias = None
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# If the clock has a "fixed-clock" compat:
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# DT_<IDENT>_CLOCKS_CLOCK_FREQUENCY_{clock_i} <CLOCK'S_FREQ>
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if "fixed-clock" in controller.compats:
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if "clock-frequency" not in controller.props:
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err(f"{controller!r} is a 'fixed-clock' but lacks a "
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"'clock-frequency' property")
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# FIXME like the CLOCK_CONTROLLER, this is missing a clock_i.
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# We need to go bug-for-bug with the previous implementation
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# to make sure there are no differences before fixing.
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prim_freq = out(f"{ident}_CLOCKS_CLOCK_FREQUENCY",
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controller.props["clock-frequency"].val)
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else:
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prim_freq = None
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out_node(node, f"CLOCK_{str2ident(name)}_{clock_i}", val,
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name_alias=clk_name_alias)
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return (prim_controller, prim_data, prim_freq)
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if "fixed-clock" not in controller.compats:
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continue
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def write_clock_other(ident, clock_i, clock, primary_cdf):
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# Write clock macros for a secondary identifier 'ident'
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if "clock-frequency" not in controller.props:
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err(f"{controller!r} is a 'fixed-clock' but lacks a "
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"'clock-frequency' property")
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prim_controller, prim_data, prim_freq = primary_cdf
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if prim_controller is not None:
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# FIXME this is replicating previous behavior that didn't
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# generate an indexed controller bug-for-bug. There's a
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# missing _{clock_i} at the end of the f-string.
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out(f"{ident}_CLOCK_CONTROLLER", prim_controller)
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for name_i, name in enumerate(clock.data.keys()):
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out(f"{ident}_CLOCK_{str2ident(name)}_{clock_i}", prim_data[name_i])
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if clock_i == 0:
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out(f"{ident}_CLOCK_{str2ident(name)}", prim_data[name_i])
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if prim_freq is not None:
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# FIXME this is also a bug-for-bug match with the previous
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# implementation.
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out(f"{ident}_CLOCKS_CLOCK_FREQUENCY", prim_freq)
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out_comment("Clock gate macros from the 'clocks' property",
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blank_before=False)
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for_each_ident(node, write_clocks_for_ident)
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out_node(node, "CLOCKS_CLOCK_FREQUENCY",
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controller.props["clock-frequency"].val)
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def str2ident(s):
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