From 6486c429f19ade94f1fd983b28906b2fbe77645d Mon Sep 17 00:00:00 2001 From: Christian Taedcke Date: Mon, 28 Oct 2019 11:36:29 +0100 Subject: [PATCH] dts: silabs: Define all available gpio ports for efr32mg12p Add device tree elements for all gpio ports of the efr32mg12p including the dts fixup entries. Also remove gpio port e since this is not available in efr32mg12p socs. Signed-off-by: Christian Taedcke --- dts/arm/silabs/efr32mg.dtsi | 32 +++++++++++++++------ soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h | 4 ++- 2 files changed, 27 insertions(+), 9 deletions(-) diff --git a/dts/arm/silabs/efr32mg.dtsi b/dts/arm/silabs/efr32mg.dtsi index bfce4514682..7824e91b814 100644 --- a/dts/arm/silabs/efr32mg.dtsi +++ b/dts/arm/silabs/efr32mg.dtsi @@ -162,14 +162,6 @@ #gpio-cells = <2>; }; - gpioe: gpio@4000a0c0 { - compatible = "silabs,efr32mg-gpio-port"; - reg = <0x4000a0c0 0x30>; - label = "GPIO_E"; - gpio-controller; - #gpio-cells = <2>; - }; - gpiof: gpio@4000a0f0 { compatible = "silabs,efr32mg-gpio-port"; reg = <0x4000a0f0 0x30>; @@ -177,6 +169,30 @@ gpio-controller; #gpio-cells = <2>; }; + + gpioi: gpio@4000a180 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a180 0x30>; + label = "GPIO_I"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioj: gpio@4000a1b0 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a1b0 0x30>; + label = "GPIO_J"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiok: gpio@4000a1e0 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a1e0 0x30>; + label = "GPIO_K"; + gpio-controller; + #gpio-cells = <2>; + }; }; }; }; diff --git a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h index 8ff92e04378..235521996f4 100644 --- a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h @@ -25,7 +25,9 @@ #define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A030_LABEL #define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A060_LABEL #define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A090_LABEL -#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A0C0_LABEL #define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A0F0_LABEL +#define DT_GPIO_GECKO_PORTI_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A180_LABEL +#define DT_GPIO_GECKO_PORTJ_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A1B0_LABEL +#define DT_GPIO_GECKO_PORTK_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A1E0_LABEL /* End of SoC Level DTS fixup file */