diff --git a/dts/arm64/nxp/nxp_mimx93_a55.dtsi b/dts/arm64/nxp/nxp_mimx93_a55.dtsi
index 89018a8de23..abc12cffee6 100644
--- a/dts/arm64/nxp/nxp_mimx93_a55.dtsi
+++ b/dts/arm64/nxp/nxp_mimx93_a55.dtsi
@@ -327,6 +327,30 @@
 		#size-cells = <0>;
 	};
 
+	flexcan1: can@443a0000 {
+		compatible = "nxp,flexcan-fd", "nxp,flexcan";
+		reg = <0x443a0000 DT_SIZE_K(64)>;
+		interrupt-parent= <&gic>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "common", "error";
+		clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
+		clk-source = <0>;
+		status = "disabled";
+	};
+
+	flexcan2: can@425b0000 {
+		compatible = "nxp,flexcan-fd", "nxp,flexcan";
+		reg = <0x425b0000 DT_SIZE_K(64)>;
+		interrupt-parent= <&gic>;
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 52 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "common", "error";
+		clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
+		clk-source = <0>;
+		status = "disabled";
+	};
+
 	edma4: dma@42000000 {
 		compatible = "nxp,edma";
 		reg = <0x42000000 (DT_SIZE_K(64) * 32)>;
diff --git a/soc/nxp/imx/imx9/imx93/a55/mmu_regions.c b/soc/nxp/imx/imx9/imx93/a55/mmu_regions.c
index 17aac7ee9ed..1052a55a5dc 100644
--- a/soc/nxp/imx/imx9/imx93/a55/mmu_regions.c
+++ b/soc/nxp/imx/imx9/imx93/a55/mmu_regions.c
@@ -32,6 +32,9 @@ static const struct arm_mmu_region mmu_regions[] = {
 	MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_kinetis_lpuart,
 						(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
 
+	MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_flexcan,
+						(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
+
 #if CONFIG_SOF
 		MMU_REGION_FLAT_ENTRY("MU2_A", DT_REG_ADDR(DT_NODELABEL(mu2_a)),
 				      DT_REG_SIZE(DT_NODELABEL(mu2_a)),