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arch/xtensa: Use ZSR assignments for stack flush markers

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The kernel coherence cache flush code was using a scratch register to
mark the top of the stack.  Likewise a good candidate for ZSR use.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2022-01-08 16:11:30 -08:00 • committed by Anas Nashif
commit 642fc7ad54
2 changed files with 3 additions and 7 deletions
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5
arch/xtensa/core/xtensa-asm2-util.S
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@ -248,11 +248,10 @@ xtensa_switch:
call0 xtensa_save_high_regs call0 xtensa_save_high_regs
#ifdef CONFIG_KERNEL_COHERENCE #ifdef CONFIG_KERNEL_COHERENCE
/* Flush the stack. The top of stack was stored for us in /* Flush the stack. The top of stack was stored for us by
* EXCSAVE3 (FIXME: shouldn't be hardcoded!) by
* arch_cohere_stacks(). It can be NULL for a dummy thread. * arch_cohere_stacks(). It can be NULL for a dummy thread.
*/ */
rsr.EXCSAVE3 a0 rsr a0, ZSR_FLUSH
beqz a0, noflush beqz a0, noflush
mov a3, a1 mov a3, a1
flushloop: flushloop:

5
arch/xtensa/include/kernel_arch_func.h
View file

@ -137,12 +137,9 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread,
z_xtensa_cache_flush((void *)osp, 1); z_xtensa_cache_flush((void *)osp, 1);
z_xtensa_cache_inv((void *)ostack, osp - ostack); z_xtensa_cache_inv((void *)ostack, osp - ostack);
/* FIXME: hardcoding EXCSAVE3 is bad, should be
* configurable a-la XTENSA_KERNEL_CPU_PTR_SR.
*/
uint32_t end = ostack + osz; uint32_t end = ostack + osz;
__asm__ volatile("wsr.EXCSAVE3 %0" :: "r"(end)); __asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(end));
} }
} }
#endif #endif