soc: neorv32: update to support NEORV32 v1.11.1
Update the NEORV32 SoC, peripheral drivers, and board to support NEORV32 v1.11.1. Notable changes include: - Optional RISC-V ISA Kconfigs are now selected on the board level. - Peripheral registers are now automatically reset in hardware, no need for software initialization code. - The NEORV32 GPIO controller now supports 32 pins, not 64. Interrupt support will be submitted in a separate PR. - Default board configuration has 64k RAM and is clocked at 18 MHz. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen
Benjamin Cabé
parent
4899cc10ac
commit
63c24d9d34
20 changed files with 340 additions and 409 deletions
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@ -1,4 +1,4 @@
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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if((CONFIG_BOARD_NEORV32) AND (CONFIG_BUILD_OUTPUT_BIN))
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@ -18,7 +18,7 @@ if((CONFIG_BOARD_NEORV32) AND (CONFIG_BUILD_OUTPUT_BIN))
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND ${IMAGE_GEN}
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ARGS -app_img
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ARGS -app_vhd
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${CONFIG_KERNEL_BIN_NAME}.bin
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${CONFIG_KERNEL_BIN_NAME}.vhd
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${PROJECT_BINARY_DIR}
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7
boards/others/neorv32/Kconfig
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7
boards/others/neorv32/Kconfig
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@ -0,0 +1,7 @@
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# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NEORV32
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select ATOMIC_OPERATIONS_C
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@ -13,7 +13,7 @@ For more information about the NEORV32, see the following websites:
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- `The NEORV32 RISC-V Processor Datasheet`_
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- `The NEORV32 RISC-V Processor User Guide`_
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The currently supported version is 1.8.6.
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The currently supported version is NEORV32 v1.11.1.
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Supported Features
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==================
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@ -27,7 +27,7 @@ using :ref:`devicetree overlays <use-dt-overlays>`.
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System Clock
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============
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The default board configuration assumes a system clock of 100 MHz. The clock
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The default board configuration assumes a system clock of 18 MHz. The clock
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frequency can be overridden by changing the ``clock-frequency`` property of the
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``cpu0`` devicetree node.
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@ -37,9 +37,10 @@ CPU
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The default board configuration assumes the NEORV32 CPU implementation has the
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following RISC-V ISA extensions enabled:
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- C (Compresses Instructions)
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- I (Base Integer Instruction Set, 32-bit)
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- M (Integer Multiplication and Division)
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- Zicsr (Control and Status Register (CSR) Instructions)
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- Zicsr (Control and Status Register (CSR) Instructions, always enabled)
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- Zifencei (Instruction-fetch fence, always enabled)
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Internal Instruction Memory
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===========================
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@ -52,7 +53,7 @@ instruction memory can be overridden by changing the ``reg`` property of the
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Internal Data Memory
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====================
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The default board configuration assumes the NEORV32 SoC implementation has a 32k
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The default board configuration assumes the NEORV32 SoC implementation has a 64k
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byte internal data memory (DMEM). The size of the data memory can be overridden
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by changing the ``reg`` property of the ``dmem`` devicetree node.
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@ -115,21 +116,21 @@ implementation with the On-Chip Debugger (OCD) and bootloader enabled.
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The default board configuration uses an :ref:`openocd-debug-host-tools`
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configuration similar to the example provided by the NEORV32 project. Other
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JTAGs can be used by providing further arguments when building. Here is an
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example for using the Flyswatter JTAG:
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JTAGs can be used by providing further arguments when flashing. Here is an
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example for using the Flyswatter JTAG @ 2 kHz:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: neorv32
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:goals: flash
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:gen-args: -DBOARD_RUNNER_ARGS_openocd="--config;interface/ftdi/flyswatter.cfg;--config;neorv32.cfg;--cmd-pre-init;'adapter speed 2000'"
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:flash-args: --config interface/ftdi/flyswatter.cfg --config neorv32.cfg --cmd-pre-init 'adapter speed 2000'
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After flashing, you should see message similar to the following in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-vn.n.nn ***
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Hello World! neorv32
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Hello World! neorv32/neorv32
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Note, however, that the application was not persisted in flash memory by the
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above steps. It was merely written to internal block RAM in the FPGA. It will
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@ -176,7 +177,7 @@ similar to the following in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-vn.n.nn ***
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Hello World! neorv32
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Hello World! neorv32/neorv32
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.. _The NEORV32 RISC-V Processor GitHub:
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https://github.com/stnolting/neorv32
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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* Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -29,25 +29,9 @@
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zephyr,uart-pipe = &uart0;
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};
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soc {
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imem: memory@0 {
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compatible = "soc-nv-flash", "mmio-sram";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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bootrom: memory@ffff0000 {
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compatible = "soc-nv-flash", "mmio-sram";
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reg = <0xffff0000 DT_SIZE_K(4)>;
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};
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dmem: memory@80000000 {
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compatible = "mmio-sram";
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reg = <0x80000000 DT_SIZE_K(32)>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led0: led0 {
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gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
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label = "LED_0";
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@ -71,7 +55,30 @@
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};
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&cpu0 {
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clock-frequency = <DT_FREQ_M(100)>;
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riscv,isa = "rv32im_zicsr_zifencei";
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clock-frequency = <DT_FREQ_M(18)>;
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};
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&bootrom {
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status = "okay";
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};
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&imem {
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status = "okay";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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&dmem {
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status = "okay";
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reg = <0x80000000 DT_SIZE_K(64)>;
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};
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&clint {
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status = "okay";
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};
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&mtimer {
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status = "okay";
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};
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&uart0 {
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@ -79,10 +86,6 @@
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current-speed = <19200>;
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};
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&gpio_lo {
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status = "okay";
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};
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&gpio_hi {
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&gpio {
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status = "okay";
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};
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@ -5,7 +5,7 @@ arch: riscv
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toolchain:
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- cross-compile
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- zephyr
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ram: 32
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ram: 64
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flash: 64
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supported:
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- gpio
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@ -1,7 +1,6 @@
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_NEORV32_ISA_C=y
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CONFIG_SERIAL=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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