diff --git a/soc/arm/st_stm32/stm32wb/CMakeLists.txt b/soc/arm/st_stm32/stm32wb/CMakeLists.txt new file mode 100644 index 00000000000..844c5252009 --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/CMakeLists.txt @@ -0,0 +1,4 @@ +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series new file mode 100644 index 00000000000..fd82f5f98ae --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series @@ -0,0 +1,15 @@ +# Kconfig - ST Microelectronics STM32WB MCU line +# +# Copyright (c) 2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_STM32WBX + +source "soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb*" + +config SOC_SERIES + default "stm32wb" + +endif # SOC_SERIES_STM32WBX diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb55xx b/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb55xx new file mode 100644 index 00000000000..5036a156639 --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb55xx @@ -0,0 +1,18 @@ +# Kconfig - ST Microelectronics STM32WB55XX MCU +# +# Copyright (c) 2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_STM32WB55XG + +config SOC + string + default "stm32wb55xx" + +config NUM_IRQS + int + default 63 + +endif # SOC_STM32WB55XG diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.series b/soc/arm/st_stm32/stm32wb/Kconfig.series new file mode 100644 index 00000000000..ee54c95e34d --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/Kconfig.series @@ -0,0 +1,17 @@ +# Kconfig - ST Microelectronics STM32WB MCU series +# +# Copyright (c) 2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_STM32WBX + bool "STM32WBx Series MCU" + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select SOC_FAMILY_STM32 + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select CPU_HAS_SYSTICK + help + Enable support for STM32WB MCU series diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.soc b/soc/arm/st_stm32/stm32wb/Kconfig.soc new file mode 100644 index 00000000000..4674a95f9f8 --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/Kconfig.soc @@ -0,0 +1,15 @@ +# Kconfig - ST Microelectronics STM32WB MCU line +# +# Copyright (c) 2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +choice + prompt "STM32WBx MCU Selection" + depends on SOC_SERIES_STM32WBX + +config SOC_STM32WB55XG + bool "STM32WB55XX" + +endchoice diff --git a/soc/arm/st_stm32/stm32wb/dts_fixup.h b/soc/arm/st_stm32/stm32wb/dts_fixup.h new file mode 100644 index 00000000000..c2888e5da5e --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/dts_fixup.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2019 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* SoC level DTS fixup file */ + +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS + +/* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32wb/linker.ld b/soc/arm/st_stm32/stm32wb/linker.ld new file mode 100644 index 00000000000..ba0abaf5051 --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/linker.ld @@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2014-2016 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/st_stm32/stm32wb/soc.c b/soc/arm/st_stm32/stm32wb/soc.c new file mode 100644 index 00000000000..ae4de3e40ca --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/soc.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for STM32WB processor + */ + +#include +#include +#include +#include + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int stm32wb_init(struct device *arg) +{ + u32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + z_clearfaults(); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + /* Update CMSIS SystemCoreClock variable (HCLK) */ + /* At reset, system core clock is set to 4 MHz from MSI */ + SystemCoreClock = 4000000; + + return 0; +} + +SYS_INIT(stm32wb_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/st_stm32/stm32wb/soc.h b/soc/arm/st_stm32/stm32wb/soc.h new file mode 100644 index 00000000000..29a7e048261 --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/soc.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the STM32WB family processors. + * + */ + + +#ifndef _STM32WBX_SOC_H_ +#define _STM32WBX_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +/* ARM CMSIS definitions must be included before kernel_includes.h. + * Therefore, it is essential to include kernel_includes.h after including + * core SOC-specific headers. + */ +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* _STM32WBX_SOC_H_ */ diff --git a/soc/arm/st_stm32/stm32wb/soc_registers.h b/soc/arm/st_stm32/stm32wb/soc_registers.h new file mode 100644 index 00000000000..542b875adec --- /dev/null +++ b/soc/arm/st_stm32/stm32wb/soc_registers.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _STM32WBX_SOC_REGISTERS_H_ +#define _STM32WBX_SOC_REGISTERS_H_ + +#endif /* _STM32WBX_SOC_REGISTERS_H_ */