From 62dbe72cb7ac55d1ae3ce62e5fb1fae47b9b293a Mon Sep 17 00:00:00 2001 From: Girisha Dengi Date: Thu, 6 Jul 2023 14:55:15 +0000 Subject: [PATCH] drivers: pm_cpu_ops: Add support for multiple PSCI versions Each PSCI interface versions have different DT compatible strings like arm,psci-0.2, arm,psci-1.1 and so on. However, the same driver can be used for all the versions by adding #define DT_COMPAT for required version and #undef DT_COMPAT for default version. Add support for PSCI cold reset, warm reset and cpu-on function IDs. Signed-off-by: Girisha Dengi Signed-off-by: Navinkumar Balabakthan --- drivers/pm_cpu_ops/CMakeLists.txt | 2 + drivers/pm_cpu_ops/Kconfig | 10 +- drivers/pm_cpu_ops/pm_cpu_ops_psci.c | 85 +++++++++++++-- drivers/pm_cpu_ops/pm_cpu_ops_psci.h | 125 ++++++++++++++++------ drivers/pm_cpu_ops/psci_shell.c | 73 +++++++++++++ dts/bindings/pm_cpu_ops/arm,psci-0.2.yaml | 14 +-- dts/bindings/pm_cpu_ops/arm,psci-1.1.yaml | 8 ++ dts/bindings/pm_cpu_ops/arm_psci.yaml | 18 ++++ include/zephyr/drivers/pm_cpu_ops.h | 14 +++ 9 files changed, 292 insertions(+), 57 deletions(-) create mode 100644 drivers/pm_cpu_ops/psci_shell.c create mode 100644 dts/bindings/pm_cpu_ops/arm,psci-1.1.yaml create mode 100644 dts/bindings/pm_cpu_ops/arm_psci.yaml diff --git a/drivers/pm_cpu_ops/CMakeLists.txt b/drivers/pm_cpu_ops/CMakeLists.txt index c738d5256bb..15643f4702a 100644 --- a/drivers/pm_cpu_ops/CMakeLists.txt +++ b/drivers/pm_cpu_ops/CMakeLists.txt @@ -5,3 +5,5 @@ zephyr_library() zephyr_library_sources_ifdef(CONFIG_PM_CPU_OPS pm_cpu_ops_weak_impl.c) zephyr_library_sources_ifdef(CONFIG_PM_CPU_OPS_PSCI pm_cpu_ops_psci.c) + +zephyr_library_sources_ifdef(CONFIG_PSCI_SHELL psci_shell.c) diff --git a/drivers/pm_cpu_ops/Kconfig b/drivers/pm_cpu_ops/Kconfig index ccab1ea78e7..712480c1d43 100644 --- a/drivers/pm_cpu_ops/Kconfig +++ b/drivers/pm_cpu_ops/Kconfig @@ -20,7 +20,7 @@ config PM_CPU_OPS_HAS_DRIVER config PM_CPU_OPS_PSCI bool "Support for the ARM Power State Coordination Interface (PSCI)" default y - depends on DT_HAS_ARM_PSCI_0_2_ENABLED + depends on DT_HAS_ARM_PSCI_0_2_ENABLED || DT_HAS_ARM_PSCI_1_1_ENABLED select PM_CPU_OPS_HAS_DRIVER help Say Y here if you want Zephyr to communicate with system firmware @@ -29,4 +29,12 @@ config PM_CPU_OPS_PSCI 0022A ("Power State Coordination Interface System Software on ARM processors"). +config PSCI_SHELL + bool "Support for PSCI interface shell commands" + default y + depends on SHELL && PM_CPU_OPS_PSCI + help + Say Y here if you need to enable PSCI interface shell commands + like 'warm' and 'cold' reset commands. + endif diff --git a/drivers/pm_cpu_ops/pm_cpu_ops_psci.c b/drivers/pm_cpu_ops/pm_cpu_ops_psci.c index 81f750ddd82..c110764e0a8 100644 --- a/drivers/pm_cpu_ops/pm_cpu_ops_psci.c +++ b/drivers/pm_cpu_ops/pm_cpu_ops_psci.c @@ -1,6 +1,8 @@ /* * Copyright 2020 Carlo Caione * + * Copyright (c) 2023, Intel Corporation. + * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,7 +21,8 @@ LOG_MODULE_REGISTER(psci); #include #include "pm_cpu_ops_psci.h" -static struct psci psci_data; +/* PSCI data object. */ +static struct psci_data_t psci_data; static int psci_to_dev_err(int ret) { @@ -80,6 +83,43 @@ int pm_system_off(void) return psci_to_dev_err(ret); } +/** + * This function checks whether the given ID is supported or not, using + * PSCI_FEATURES command.PSCI_FEATURES is supported from version 1.0 onwards. + */ +static int psci_features_check(unsigned long function_id) +{ + /* PSCI_FEATURES function ID is supported from PSCI 1.0 onwards. */ + if (!(PSCI_VERSION_MAJOR(psci_data.ver) >= 1)) { + LOG_ERR("Function ID %lu not supported", function_id); + return -ENOTSUP; + } + + return psci_data.invoke_psci_fn(PSCI_FN_NATIVE(1_0, PSCI_FEATURES), function_id, 0, 0); +} + +int pm_system_reset(unsigned char reset_type) +{ + int ret; + + if (psci_data.conduit == SMCCC_CONDUIT_NONE) { + return -EINVAL; + } + + if ((reset_type == SYS_WARM_RESET) && + (!psci_features_check(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2)))) { + ret = psci_data.invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), 0, 0, 0); + } else if (reset_type == SYS_COLD_RESET) { + ret = psci_data.invoke_psci_fn(PSCI_FN_NATIVE(0_2, SYSTEM_RESET), 0, 0, 0); + } else { + LOG_ERR("Invalid system reset type issued"); + return -EINVAL; + } + + return psci_to_dev_err(ret); + +} + static unsigned long __invoke_psci_fn_hvc(unsigned long function_id, unsigned long arg0, unsigned long arg1, @@ -107,16 +147,14 @@ static uint32_t psci_get_version(void) return psci_data.invoke_psci_fn(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0); } -static int set_conduit_method(void) +static int set_conduit_method(const struct device *dev) { - const char *method; + const struct psci_config_t *dev_config = (const struct psci_config_t *)dev->config; - method = DT_PROP(DT_INST(0, DT_DRV_COMPAT), method); - - if (!strcmp("hvc", method)) { + if (!strcmp("hvc", dev_config->method)) { psci_data.conduit = SMCCC_CONDUIT_HVC; psci_data.invoke_psci_fn = __invoke_psci_fn_hvc; - } else if (!strcmp("smc", method)) { + } else if (!strcmp("smc", dev_config->method)) { psci_data.conduit = SMCCC_CONDUIT_SMC; psci_data.invoke_psci_fn = __invoke_psci_fn_smc; } else { @@ -154,13 +192,38 @@ static int psci_init(const struct device *dev) { psci_data.conduit = SMCCC_CONDUIT_NONE; - if (set_conduit_method()) { + if (set_conduit_method(dev)) { return -ENOTSUP; } return psci_detect(); } -DEVICE_DT_INST_DEFINE(0, psci_init, NULL, - &psci_data, NULL, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, - NULL); +/** + * Each PSCI interface versions have different DT compatible strings like arm,psci-0.2, + * arm,psci-1.1 and so on. However, the same driver can be used for all the versions with + * the below mentioned DT method where we need to #undef the default version arm,psci-0.2 + * and #define the required version like arm,psci-1.0 or arm,psci-1.1. + */ +#define PSCI_DEFINE(inst, ver) \ + static const struct psci_config_t psci_config_##inst##ver = { \ + .method = DT_PROP(DT_DRV_INST(inst), method) \ + }; \ + DEVICE_DT_INST_DEFINE(inst, \ + &psci_init, \ + NULL, \ + &psci_data, \ + &psci_config_##inst##ver, \ + PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ + NULL); + +#define PSCI_0_2_INIT(n) PSCI_DEFINE(n, PSCI_0_2) +#undef DT_DRV_COMPAT +#define DT_DRV_COMPAT arm_psci_0_2 +DT_INST_FOREACH_STATUS_OKAY(PSCI_0_2_INIT) + +#define PSCI_1_1_INIT(n) PSCI_DEFINE(n, PSCI_1_1) +#undef DT_DRV_COMPAT +#define DT_DRV_COMPAT arm_psci_1_1 +DT_INST_FOREACH_STATUS_OKAY(PSCI_1_1_INIT) diff --git a/drivers/pm_cpu_ops/pm_cpu_ops_psci.h b/drivers/pm_cpu_ops/pm_cpu_ops_psci.h index f06b369ee46..606071fbb07 100644 --- a/drivers/pm_cpu_ops/pm_cpu_ops_psci.h +++ b/drivers/pm_cpu_ops/pm_cpu_ops_psci.h @@ -10,55 +10,112 @@ #include #ifdef CONFIG_64BIT -#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name +#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name #else -#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name +#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name #endif /* PSCI v0.2 interface */ -#define PSCI_0_2_FN_BASE 0x84000000 -#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) -#define PSCI_0_2_64BIT 0x40000000 -#define PSCI_0_2_FN64_BASE \ - (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) -#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) +#define PSCI_0_2_FN_BASE 0x84000000 +#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) +#define PSCI_0_2_64BIT 0x40000000 +#define PSCI_0_2_FN64_BASE (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) +#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) +#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) +#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) +#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) +#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) +#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) +#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) +#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) +#define PSCI_0_2_FN64_SYSTEM_RESET PSCI_0_2_FN(9) -#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) -#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) -#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) -#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) -#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) -#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) -#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) -#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) -#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) -#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) +/* PSCI v1.0 interface */ +#define PSCI_1_0_FN_BASE (0x84000000U) +#define PSCI_1_0_64BIT (0x40000000U) +#define PSCI_1_0_FN64_BASE (PSCI_1_0_FN_BASE + PSCI_1_0_64BIT) +#define PSCI_1_0_FN(n) (PSCI_1_0_FN_BASE + (n)) +#define PSCI_1_0_FN64(n) (PSCI_1_0_FN64_BASE + (n)) +#define PSCI_1_0_FN_PSCI_VERSION PSCI_1_0_FN(0) +#define PSCI_1_0_FN_CPU_SUSPEND PSCI_1_0_FN(1) +#define PSCI_1_0_FN_CPU_OFF PSCI_1_0_FN(2) +#define PSCI_1_0_FN_CPU_ON PSCI_1_0_FN(3) +#define PSCI_1_0_FN_AFFINITY_INFO PSCI_1_0_FN(4) +#define PSCI_1_0_FN_MIGRATE PSCI_1_0_FN(5) +#define PSCI_1_0_FN_MIGRATE_INFO_TYPE PSCI_1_0_FN(6) +#define PSCI_1_0_FN_MIGRATE_INFO_UP_CPU PSCI_1_0_FN(7) +#define PSCI_1_0_FN_SYSTEM_OFF PSCI_1_0_FN(8) +#define PSCI_1_0_FN_SYSTEM_RESET PSCI_1_0_FN(9) +#define PSCI_1_0_FN_PSCI_FEATURES PSCI_1_0_FN(10) +#define PSCI_1_0_FN64_CPU_SUSPEND PSCI_1_0_FN64(1) +#define PSCI_1_0_FN64_CPU_ON PSCI_1_0_FN64(3) +#define PSCI_1_0_FN64_AFFINITY_INFO PSCI_1_0_FN64(4) +#define PSCI_1_0_FN64_MIGRATE PSCI_1_0_FN64(5) +#define PSCI_1_0_FN64_MIGRATE_INFO_UP_CPU PSCI_1_0_FN64(7) +/* PSCI function ID is same for both 32 and 64 bit.*/ +#define PSCI_1_0_FN64_SYSTEM_RESET PSCI_1_0_FN(9) +#define PSCI_1_0_FN64_PSCI_FEATURES PSCI_1_0_FN(10) -#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) -#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) -#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) -#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) -#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) +/* PSCI v1.1 interface. */ +#define PSCI_1_1_FN_BASE (0x84000000U) +#define PSCI_1_1_64BIT (0x40000000U) +#define PSCI_1_1_FN64_BASE (PSCI_1_1_FN_BASE + PSCI_1_1_64BIT) +#define PSCI_1_1_FN(n) (PSCI_1_1_FN_BASE + (n)) +#define PSCI_1_1_FN64(n) (PSCI_1_1_FN64_BASE + (n)) +#define PSCI_1_1_FN_PSCI_VERSION PSCI_1_1_FN(0) +#define PSCI_1_1_FN_CPU_SUSPEND PSCI_1_1_FN(1) +#define PSCI_1_1_FN_CPU_OFF PSCI_1_1_FN(2) +#define PSCI_1_1_FN_CPU_ON PSCI_1_1_FN(3) +#define PSCI_1_1_FN_AFFINITY_INFO PSCI_1_1_FN(4) +#define PSCI_1_1_FN_MIGRATE PSCI_1_1_FN(5) +#define PSCI_1_1_FN_MIGRATE_INFO_TYPE PSCI_1_1_FN(6) +#define PSCI_1_1_FN_MIGRATE_INFO_UP_CPU PSCI_1_1_FN(7) +#define PSCI_1_1_FN_SYSTEM_OFF PSCI_1_1_FN(8) +#define PSCI_1_1_FN_SYSTEM_RESET PSCI_1_1_FN(9) +#define PSCI_1_1_FN_PSCI_FEATURES PSCI_1_1_FN(10) +#define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_1_1_FN(18) +#define PSCI_1_1_FN64_CPU_SUSPEND PSCI_1_1_FN64(1) +#define PSCI_1_1_FN64_CPU_ON PSCI_1_1_FN64(3) +#define PSCI_1_1_FN64_AFFINITY_INFO PSCI_1_1_FN64(4) +#define PSCI_1_1_FN64_MIGRATE PSCI_1_1_FN64(5) +#define PSCI_1_1_FN64_MIGRATE_INFO_UP_CPU PSCI_1_1_FN64(7) +/* PSCI function ID is same for both 32 and 64 bit.*/ +#define PSCI_1_1_FN64_SYSTEM_RESET PSCI_1_1_FN(9) +#define PSCI_1_1_FN64_PSCI_FEATURES PSCI_1_1_FN(10) +#define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_1_1_FN64(18) /* PSCI return values (inclusive of all PSCI versions) */ -#define PSCI_RET_SUCCESS 0 -#define PSCI_RET_NOT_SUPPORTED -1 -#define PSCI_RET_INVALID_PARAMS -2 -#define PSCI_RET_DENIED -3 -#define PSCI_RET_ALREADY_ON -4 -#define PSCI_RET_ON_PENDING -5 -#define PSCI_RET_INTERNAL_FAILURE -6 -#define PSCI_RET_NOT_PRESENT -7 -#define PSCI_RET_DISABLED -8 -#define PSCI_RET_INVALID_ADDRESS -9 +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_SUPPORTED -1 +#define PSCI_RET_INVALID_PARAMS -2 +#define PSCI_RET_DENIED -3 +#define PSCI_RET_ALREADY_ON -4 +#define PSCI_RET_ON_PENDING -5 +#define PSCI_RET_INTERNAL_FAILURE -6 +#define PSCI_RET_NOT_PRESENT -7 +#define PSCI_RET_DISABLED -8 +#define PSCI_RET_INVALID_ADDRESS -9 typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long, unsigned long); -struct psci { +struct psci_data_t { enum arm_smccc_conduit conduit; psci_fn *invoke_psci_fn; uint32_t ver; }; +/* PSCI configuration data. */ +struct psci_config_t { + const char *method; +}; + #endif /* ZEPHYR_DRIVERS_PSCI_PSCI_H_ */ diff --git a/drivers/pm_cpu_ops/psci_shell.c b/drivers/pm_cpu_ops/psci_shell.c new file mode 100644 index 00000000000..34669b65a08 --- /dev/null +++ b/drivers/pm_cpu_ops/psci_shell.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* Zephyr kernel start address. */ +extern void __start(void); + +static int cmd_reboot_warm(const struct shell *shctx, size_t argc, char **argv) +{ + ARG_UNUSED(shctx); + ARG_UNUSED(argc); + ARG_UNUSED(argv); + int ret; + + ret = pm_system_reset(SYS_WARM_RESET); + if (ret != 0) { + shell_error(shctx, "Failed to perform system warm reset"); + } + + return ret; +} + +static int cmd_reboot_cold(const struct shell *shctx, size_t argc, char **argv) +{ + ARG_UNUSED(shctx); + ARG_UNUSED(argc); + ARG_UNUSED(argv); + int ret; + + ret = pm_system_reset(SYS_COLD_RESET); + if (ret != 0) { + shell_error(shctx, "Failed to perform system cold reset"); + } + + return ret; +} + +static int cmd_psci_cpuon(const struct shell *shctx, size_t argc, char **argv) +{ + ARG_UNUSED(shctx); + ARG_UNUSED(argc); + long cpu_id; + int result; + + errno = 0; + cpu_id = strtol(argv[1], NULL, 10); + if (cpu_id == 0 || cpu_id == LONG_MIN || cpu_id == LONG_MAX) { + if (errno != 0) { + shell_error(shctx, "psci: invalid input:%ld", cpu_id); + return -EINVAL; + } + } + + result = pm_cpu_on((unsigned long)cpu_id, (uintptr_t)&__start); + + return result; +} + +SHELL_STATIC_SUBCMD_SET_CREATE( + sub_reboot, + SHELL_CMD_ARG(warm, NULL, "System warm reset. Usage: ", cmd_reboot_warm, 1, 0), + SHELL_CMD_ARG(cold, NULL, "System cold reset. Usage: ", cmd_reboot_cold, 1, 0), + SHELL_CMD_ARG(cpuon, NULL, "Power-up the secondary CPU. Usage: >", + cmd_psci_cpuon, 2, 0), + SHELL_SUBCMD_SET_END /* Array terminated. */ +); + +SHELL_CMD_REGISTER(psci, &sub_reboot, "ARM PSCI interface commands", NULL); diff --git a/dts/bindings/pm_cpu_ops/arm,psci-0.2.yaml b/dts/bindings/pm_cpu_ops/arm,psci-0.2.yaml index ebebb1ea5e7..0d7c1a82a8c 100644 --- a/dts/bindings/pm_cpu_ops/arm,psci-0.2.yaml +++ b/dts/bindings/pm_cpu_ops/arm,psci-0.2.yaml @@ -1,17 +1,9 @@ # Copyright (c) 2020 Carlo Caione +# Copyright (c) 2023, Intel Corporation # SPDX-License-Identifier: Apache-2.0 -description: PSCI +description: Power State Coordination Interface (PSCI) version 0.2. compatible: "arm,psci-0.2" -include: base.yaml - -properties: - method: - type: string - required: true - description: The method of calling the PSCI firmware. - enum: - - smc - - hvc +include: arm_psci.yaml diff --git a/dts/bindings/pm_cpu_ops/arm,psci-1.1.yaml b/dts/bindings/pm_cpu_ops/arm,psci-1.1.yaml new file mode 100644 index 00000000000..507e4f827f8 --- /dev/null +++ b/dts/bindings/pm_cpu_ops/arm,psci-1.1.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2023, Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Power State Coordination Interface (PSCI) version 1.1. + +compatible: "arm,psci-1.1" + +include: arm_psci.yaml diff --git a/dts/bindings/pm_cpu_ops/arm_psci.yaml b/dts/bindings/pm_cpu_ops/arm_psci.yaml new file mode 100644 index 00000000000..3852d627f4b --- /dev/null +++ b/dts/bindings/pm_cpu_ops/arm_psci.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2023, Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: This Power State Coordination Interface (PSCI) defines a standard + interface for power management that can be used by operating system + vendors, for supervisory software working at different levels of + privilege on an ARM device. + +include: base.yaml + +properties: + method: + type: string + required: true + description: The method of calling the PSCI firmware. + enum: + - smc + - hvc diff --git a/include/zephyr/drivers/pm_cpu_ops.h b/include/zephyr/drivers/pm_cpu_ops.h index 3e1e6a51a01..49ea67e155c 100644 --- a/include/zephyr/drivers/pm_cpu_ops.h +++ b/include/zephyr/drivers/pm_cpu_ops.h @@ -20,6 +20,9 @@ extern "C" { #endif +/* System reset types. */ +#define SYS_WARM_RESET 0 +#define SYS_COLD_RESET 1 /** * @defgroup power_management_cpu_api CPU Power Management * @ingroup subsys_pm @@ -65,6 +68,17 @@ int pm_cpu_on(unsigned long cpuid, uintptr_t entry_point); */ int pm_system_off(void); +/** + * @brief System reset + * + * This function provides a method for performing a system cold or warm reset. + * + * @param reset system reset type, cold or warm. + * + * @retval 0 on success, a negative errno otherwise + */ +int pm_system_reset(unsigned char reset); + #ifdef __cplusplus } #endif